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PRELIMINARY DATA SHEET
MOS INTEGRATED CIRCUIT
EDD1204ALTA, EDD1208ALTA, EDD1216ALTA
128 M-bit Synchronous DRAM with Double Data Rate (4-bank, SSTL_2)
Description The EDD1204ALTA, EDD1208ALTA, EDD1216ALTA are high-speed 134,217,728 bits synchronous dynamic random-access memories, organized as 8,388,608x4x4, 4,194,304x8x4, 2,097,152x16x4 (word x bit x bank), respectively. The synchronous DRAMs use Double Data Rate (DDR) where data bandwidth is twice of regular synchronous DRAM. The synchronous DRAM is compatible with SSTL_2 (Stub Series terminated Logic for 2.5 V). The synchronous DRAM is packaged in 66-pin Plastic TSOP (II). Features * Fully Synchronous Dynamic RAM with all input signals except DM, DQS and DQ referenced to a positive clock edge * Double Data Rate interface Differential CLK (/CLK) input Data inputs and DM are synchronized with both edges of DQS Data outputs and DQS are synchronized with a cross point of CLK and /CLK * Quad internal banks operation * Possible to assert random column address in every clock cycle * Programmable Mode register set /CAS latency (2, 2.5) Burst length (2, 4, 8) Wrap sequence (Sequential / Interleave) * Automatic precharge and controlled precharge * CBR (Auto) refresh and self refresh * x4, x8, x16 organization * Byte write control (x4, x8) by DM * Byte write control (x16) by LDM and UDM * 2.5 V 0.2 V Power supply for VDD * 2.5 V 0.2 V Power supply for VDDQ * Maximum clock frequency up to 133 MHz * SSTL_2 compatible with all signals * 4,096 refresh cycles/64 ms * 66-pin Plastic TSOP (II) (10.16 mm (400)) * Burst termination by Precharge command and Burst stop command
The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.
Not all devices/types available in every country. Please check with local Elpida Memory, Inc. for availability and additional information.
Document No. E0136E30 (Ver. 3.0) Date Published October 2001 (K) Printed in Japan
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.
EDD1204ALTA, EDD1208ALTA, EDD1216ALTA
Ordering Information
Part Number Organization (word x bit x bank) EDD1204ALTA-7A EDD1204ALTA-75 EDD1204ALTA-1A EDD1208ALTA-7A EDD1208ALTA-75 EDD1208ALTA-1A EDD1216ALTA-7A EDD1216ALTA-75 EDD1216ALTA-1A 2M x 16 x 4 4M x 8 x 4 8M x 4 x 4 Clock frequency MHz (MAX.) 133 133 100 133 133 100 133 133 100 66-pin Plastic TSOP (II) (10.16 mm (400)) Package
2
Preliminary Data Sheet E0136E30
EDD1204ALTA, EDD1208ALTA, EDD1216ALTA
Part Number
E D D 12 04 A L TA - 7A
ELPIDA Memory Material Type D: Mono Function D: DDR (I) Density & Bank 12: 128M/4 Bank Bit Organization 4: x4 8: x8 16: x16 Interface A: SSTL_2 Mask Revision Package TA: TSOP (II) Speed 7A: 7.5 ns (133 MHz) 75: 7.5 ns (133 MHz) 1A: 10 ns (100 MHz)
Preliminary Data Sheet E0136E30
3
EDD1204ALTA, EDD1208ALTA, EDD1216ALTA
Pin Configurations /xxx indicates active low signal. [EDD1204ALTA] 66-pin Plastic TSOP (II) (10.16 mm (400)) 8M word x 4 bit x 4 bank
VDD NC VDDQ NC DQ0 VSSQ NC NC VDDQ NC DQ1 VSSQ NC NC VDDQ NC NC VDD NC NC /WE /CAS /RAS /CS NC BA0 BA1 A10/AP A0 A1 A2 A3 VDD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33
66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34
VSS NC VSSQ NC DQ3 VDDQ NC NC VSSQ NC DQ2 VDDQ NC NC VSSQ DQS NC VREF VSS DM /CLK CLK CKE NC NC A11 A9 A8 A7 A6 A5 A4 VSS
A0 - A11 A0 - A11 BA0, BA1 DQ0 - DQ3 DQS CLK, /CLK CKE /CS /RAS
: Address inputs : Row address inputs : Bank select : Data inputs/outputs : Data strobe : System clock input : Clock enable : Chip select : Row address strobe
/CAS /WE DM VDD VSS VDDQ VSSQ VREF NC
: Column address strobe : Write enable : DQ write mask enable : Supply voltage : Ground : Supply voltage for DQ and DQS : Ground for DQ and DQS : Input reference : No connection
A0 - A9, A11 : Column address inputs
4
Preliminary Data Sheet E0136E30
EDD1204ALTA, EDD1208ALTA, EDD1216ALTA
[EDD1208ALTA] 66-pin Plastic TSOP (II) (10.16 mm (400)) 4M word x 8 bit x 4 bank
VDD DQ0 VDDQ NC DQ1 VSSQ NC DQ2 VDDQ NC DQ3 VSSQ NC NC VDDQ NC NC VDD NC NC /WE /CAS /RAS /CS NC BA0 BA1 A10/AP A0 A1 A2 A3 VDD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33
66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34
VSS DQ7 VSSQ NC DQ6 VDDQ NC DQ5 VSSQ NC DQ4 VDDQ NC NC VSSQ DQS NC VREF VSS DM /CLK CLK CKE NC NC A11 A9 A8 A7 A6 A5 A4 VSS
A0 - A11 A0 - A11 A0 - A9 BA0, BA1 DQ0 - DQ7 DQS CLK, /CLK CKE /CS /RAS
: Address inputs : Row address inputs : Column address inputs : Bank select : Data inputs/outputs : Data strobe : System clock input : Clock enable : Chip select : Row address strobe
/CAS /WE DM VDD VSS VDDQ VSSQ VREF NC
: Column address strobe : Write enable : DQ write mask enable : Supply voltage : Ground : Supply voltage for DQ and DQS : Ground for DQ and DQS : Input reference : No connection
Preliminary Data Sheet E0136E30
5
EDD1204ALTA, EDD1208ALTA, EDD1216ALTA
[EDD1216ALTA] 66-pin Plastic TSOP (II) (10.16 mm (400)) 2M word x 16bit x 4 bank
VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 NC VDDQ LDQS NC VDD NC LDM /WE /CAS /RAS /CS NC BA0 BA1 A10/AP A0 A1 A2 A3 VDD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33
66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34
VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 NC VSSQ UDQS NC VREF VSS UDM /CLK CLK CKE NC NC A11 A9 A8 A7 A6 A5 A4 VSS
A0 - A11 A0 - A11 A0 - A8 BA0, BA1 DQ0 - DQ15 CLK, /CLK CKE /CS /RAS
: Address inputs : Row address inputs : Column address inputs : Bank select : Data inputs/outputs : System clock input : Clock enable : Chip select : Row address strobe
/CAS /WE LDM, UDM VDD VSS VDDQ VSSQ VREF NC
: Column address strobe : Write enable : DQ write mask enable : Supply voltage : Ground : Supply voltage for DQ, LDQS and UDQS : Ground for DQ, LDQS and UDQS : Input reference : No connection
LDQS, UDQS : Data strobe
6
Preliminary Data Sheet E0136E30
EDD1204ALTA, EDD1208ALTA, EDD1216ALTA
Block Diagram
CLK /CLK CKE
Clock Generator
Bank D Bank C Bank B
A0 - A11, BA0, BA1
Mode Register
Row Address Buffer and Refresh Counter
Row Decoder
Memory Cell Array Bank A
Sense Amp.
Command Decoder
/CS /RAS /CAS /WE
Column Address Buffer and Burst Counter
Control Logic
Column Decoder
Data Control Circuit
Latch Circuit
DQS
CLK, /CLK
DLL
Input & Output Buffer
DM
DQ
Preliminary Data Sheet E0136E30
7
EDD1204ALTA, EDD1208ALTA, EDD1216ALTA
CONTENTS
1. Input/Output Pin Function....................................................................................................................................10
2. Commands ............................................................................................................................................................11
3. Simplified State Diagram......................................................................................................................................15
4. Truth Table ............................................................................................................................................................16 4.1 Command Truth Table...............................................................................................................................16 4.2 DM Truth Table ..........................................................................................................................................16 4.3 CKE Truth Table ........................................................................................................................................16 4.4 Operative Command Table
Note1
................................................................................................................17
4.5 Command Truth Table for CKE .................................................................................................................20
5. Initialization ...........................................................................................................................................................21
6. Programming the Mode Register.........................................................................................................................22
7. Mode Register .......................................................................................................................................................23 7.1 Burst Length and Sequence ......................................................................................................................24
8. Address Bits of Bank-Select and Precharge ......................................................................................................25
9. Precharge ..............................................................................................................................................................26 9.1 Read to Precharge Command Interval ......................................................................................................26 9.2 Write to Precharge Command Interval ......................................................................................................27
10. Auto Precharge ...................................................................................................................................................28 10.1 Read with Auto Precharge.......................................................................................................................28 10.2 Write with Auto Precharge.......................................................................................................................29
11. Read/Write Command Interval ...........................................................................................................................30 11.1 Read to Read Command Interval ............................................................................................................30 11.2 Write to Write Command Interval ............................................................................................................31 11.3 Write to Read Command Interval ............................................................................................................32 11.4 Read to Write Command Interval ............................................................................................................33 8
Preliminary Data Sheet E0136E30
EDD1204ALTA, EDD1208ALTA, EDD1216ALTA
12. Burst Termination ...............................................................................................................................................34 12.1 Burst Stop Command in Read Cycle .......................................................................................................34 12.2 Terminating a Burst Read Cycle by Precharge Command ......................................................................35 12.3 Terminating a Burst Write Cycle by Precharge Command ......................................................................36
13. Electrical Specifications.....................................................................................................................................37 13.1 Absolute Maximum Ratings .....................................................................................................................37 13.2 Recommended Operating Conditions......................................................................................................37 13.3 Pin Capacitance (TA = 25 C, f = 100 MHz) .............................................................................................37 13.4 DC Characteristics 1 (Recommended Operating Conditions unless otherwise noted) ...........................38 13.5 DC Characteristics 2 (Recommended Operating Conditions unless otherwise noted) ...........................39 13.6 AC Characteristics (Recommended Operating Conditions unless otherwise noted)...............................39 13.6.1 Test Conditions .........................................................................................................................39 13.6.2 Timing Diagram .........................................................................................................................40 13.6.3 Synchronous Characteristics.....................................................................................................41 13.6.4 Synchronous Characteristics Example......................................................................................42 13.6.5 Asynchronous Characteristics...................................................................................................42
14. Package Drawing ................................................................................................................................................74
15. Recommended Soldering Conditions ...............................................................................................................75
16. Revision History..................................................................................................................................................76
Preliminary Data Sheet E0136E30
9
EDD1204ALTA, EDD1208ALTA, EDD1216ALTA
1. Input/Output Pin Function
Pin name CLK, /CLK
Input/Output Input
Function CLK and /CLK are the master clock inputs. The timing reference point for the differential clock is when CLK and /CLK cross. All control and address inputs except for DQ and DM are latched by a rising edge of CLK. By both of rising and falling edges of CLK, output DQ and DQS are validated.
CKE
Input
CKE controls power down mode. When the EDD12xxALTA is not in burst mode and CKE is negated, the device enters power down mode and deactivates internal clock signals, input buffers and output drivers. During power down mode, CKE must remain low. /CS low starts a command input cycle. When /CS is high, commands are ignored but the current operations will be continued. As well as regular SDRAMs, each combination of /RAS, /CAS, and /WE input in conjunction with /CS input at a rising edge of CLK determines SDRAM operation. Refer to the command table. Row address is determined by A0 - A11 at the rising edge of CLK in active command cycle. It does not depend on the bit organization. Column address is determined by A0 - A9, A11 at the rising edge of CLK in read or write command cycle. It depends on the bit organization: A0 - A9, A11 for x4 device, A0 - A9 for x8 device, A0 - A8 for x16 device. A10 defines precharge mode. When A10 is high in precharge command cycle, all banks are precharged; when A10 is low, only the bank selected by BA0 and BA1 is precharged. When A10 is high in read or write command cycle, precharge starts automatically after the burst access.
/CS /RAS, /CAS, /WE A0 - A11
Input Input
Input
BA0, BA1
Input
BA0, BA1 are bank select signals. In command cycle, BA0 and BA1 low select Bank A, BA0 high and BA1 low select bank B, BA0 low and BA1 high select bank C and then BA0 and BA1 high select bank D. DQ pins have the same function as I/O pins on conventional DRAMs. Active on the both edges for data input and output. DM's are latched by both of rising and falling edges of the DQS. In write mode, DM's control byte mask. Unlike regular SDRAMs, DM's do not control read operation. VREF is reference voltage for SSTL input buffers.
DQ0 - DQ15 DQS, LDQS, UDQS DM, LDM, UDM VREF VDD, VDDQ, VSS, VSSQ
Input/Output Input/Output Input Input
(Power Supply) VDD and VSS are power supply pins for internal circuits. VDDQ and VSSQ are power supply pins for the output buffers.
10
Preliminary Data Sheet E0136E30
EDD1204ALTA, EDD1208ALTA, EDD1216ALTA
2. Commands
Extended mode register set command (/CS, /RAS, /CAS, /WE Low)
Fig.1 Extended mode register set command
CLK
The EDD12xxALTA has an extended mode register that defines enabling or disabling DLL. In this command, A0 through A11, BA0 and BA1 are the data input pins. After power on, the extended mode register set command must be executed for enabling or disabling DLL. The extended mode register can be set only when all banks are in idle state. During tMRD, the EDD12xxALTA can not accept any other commands.
CKE /CS /RAS /CAS /WE BA0 BA1 A10 Add
H
Mode register set command (/CS, /RAS, /CAS, /WE Low) The EDD12xxALTA has a mode register that defines how the device operates. In this command, A0 through A11, BA0 and BA1 are the data input pins. After power on, the mode register set command must be executed to initialize the device. The mode register can be set only when all banks are in idle state. During tMRD, the EDD12xxALTA can not accept any other commands.
Fig.2 Mode register set command
CLK CKE /CS /RAS /CAS /WE BA0,BA1 A10 Add H
Bank activate command (/CS, /RAS = Low, /CAS, /WE = High) The EDD12xxALTA has four banks, each with 4,096 rows. This command activates the bank and the row address selected by BA0 and BA1, and by A0 through A11 respectively. This command corresponds to a conventional DRAM's /RAS falling.
Fig.3 Bank activate command
CLK CKE /CS /RAS /CAS /WE BA0,BA1 A10 Add Row Row H
Preliminary Data Sheet E0136E30
11
EDD1204ALTA, EDD1208ALTA, EDD1216ALTA
Precharge command (/CS, /RAS, /WE= Low, /CAS = High) This command begins precharge operation of the bank selected by BA0, BA1 and A10. When A10 is High, all banks are precharged, regardless of BA0 and BA1. When A10 is Low, only the bank selected by BA0 and BA1 is precharged. After this command, the EDD12xxALTA can't accept the activate command to the precharging bank during tRP (precharge to activate command period). This command can terminate the current burst operation. This command corresponds to a conventional DRAM's /RAS rising.
Fig.4 Precharge command
CLK CKE /CS /RAS /CAS /WE BA0, BA1 A10
(Precharge select)
H
Add
Read command (/CS, /CAS = Low, /RAS, /WE = High)
Fig.5 Read command
CLK
This command begins the burst read operation. The bank and the burst start column address are selected by BA0 and BA1 and by A0 through A11 respectively. Read data is available after /CAS latency requirements which have been met. And it is synchronized with DQS.
CKE /CS /RAS /CAS /WE BA0, BA1 A10
(Auto precharge select)
H
Add
Col.
Write command (/CS, /CAS, /WE = Low, /RAS = High) This command begins burst write operation. The bank and the burst start column address are selected by BA0 and BA1 and by A0 through A11 respectively. Write data must be input by DQ0 through DQ15. Byte mask data must be input by DM, LDM, and UDM. Both data must be synchronized with DQS that is inputted after this command.
Fig.6 Write command
CLK CKE /CS /RAS /CAS /WE BA0, BA1 A10
(Auto precharge select)
H
Add
Col.
12
Preliminary Data Sheet E0136E30
EDD1204ALTA, EDD1208ALTA, EDD1216ALTA
CBR (auto) refresh command (/CS, /RAS, /CAS = Low, /WE, CKE = High)
Fig.7 CBR (auto) refresh command
CLK
This command is a request to begin the CBR (auto) refresh operation. The refresh address is generated internally. Before executing CBR (auto) refresh, all banks must be precharged. After this cycle, all banks will be in the idle (precharged) state and ready for a bank activate command. During tRFC (refresh command to refresh or activate command period), the EDD12xxALTA cannot accept any other command.
CKE /CS /RAS /CAS /WE BA0, BA1 A10 Add
H
Self refresh entry command (/CS, /RAS, /CAS, CKE = Low, /WE = High) After the command execution, self refresh operation continues while CKE remains low. When CKE goes high, the EDD12xxALTA will exit the self refresh mode. During self refresh mode, refresh interval and refresh operation are performed internally, so there is no need for external control. Before executing self refresh, all banks must be precharged.
Fig.8 Self refresh entry command
CLK CKE /CS /RAS /CAS /WE BA0, BA1 A10 Add
Burst stop command (/CS, /WE = Low, /RAS, /CAS = High) This command can stop the current read burst operation.
Fig.9 Burst stop command
CLK CKE /CS /RAS /CAS /WE BA0, BA1 A10 Add H
Preliminary Data Sheet E0136E30
13
EDD1204ALTA, EDD1208ALTA, EDD1216ALTA
No operation (/CS = Low, /RAS, /CAS, /WE = High) This command is not an execution command. This command doesn't begin or terminate any operation.
Fig.10 No operation
CLK CKE /CS /RAS /CAS /WE BA0, BA1 A10 Add H
14
Preliminary Data Sheet E0136E30
EDD1204ALTA, EDD1208ALTA, EDD1216ALTA
3. Simplified State Diagram
Self Refresh Recovery
SELF
SREX
Self Refresh
Mode Register Set
MRS, EMRS IDLE
REF
CBR (auto) Refresh
(tMRD)
PW PDE DN
ACT
(tRFC)
X
Bank Activating
DN
PD EX
Power Down
PW
BANK ACTIVE
RE
PRE/PALL
BS AD
st
T
RE
ITA
(B
WR
(tW
R)
ur
AD A
en
d)
READ WRIT WRIT READ
RE
READ
AD
A
READA
PR E( Pre ch arg et erm ina tion (B ur ) st en d)
PR E(
WRITA
READA
Pre ch arg et erm ina
(tW
R/
tio
tD
n)
AL
)
Precharge
PRE/PALL
POWER ON
(tRP)
Automatic sequence Manual input
Preliminary Data Sheet E0136E30
15
EDD1204ALTA, EDD1208ALTA, EDD1216ALTA
4. Truth Table
4.1 Command Truth Table
Function Symbol n-1 Device deselect No operation Burst stop Read Read with auto precharge Write Write with auto precharge Bank active Prechrage select bank Precharge all banks Mode register set Extended mode register set DESL NOP BST READ READA WRIT WRITA ACT PRE PALL MRS EMRS H x L L L L L H H H x x L L L L H H H L V x L L H x L H L L V H H H H CKE n x x x x H L L L x H H H x H H L x H L H /CS /RAS /CAS /WE BA0 BA1 x x x V Address A10 x x x L H L H V L H L L x x V V V A0-9,A11 x x x V
4.2 DM Truth Table
Function Symbol n-1 Data write enable Data mask Upper byte write enable Lower byte write enable Upper byte write inhibit Lower byte write inhibit ENB MASK ENBU ENBL MASKU MASKL H H H H H H CKE n x x x x x x L x H x U L H x L x H DM L
4.3 CKE Truth Table
Current State Function Symbol n-1 Idle Idle Self refresh CBR (auto) refresh command Self refresh entry Self refresh exit REF SELF SREX H H L CKE n H L H H L Idle Power down entry PWDN H L H L Bank(s) active Power down entry PWDN H L H L Power down Power down exit PDEX L H H L x H x H x H x H x H x H x H x H x x x x x x x x x x x x x x x x L L L H x /CS /RAS /CAS /WE Address
Remark H = High level, L = Low level, V = Valid, x = High or Low level (Don't care)
16
Preliminary Data Sheet E0136E30
EDD1204ALTA, EDD1208ALTA, EDD1216ALTA
4.4 Operative Command Table
Current state Idle
Note1
(1/3)
/CS /RAS /CAS /WE H L L L L L L L L L Row active H L L L L L L L L L Read H L L L x H H H H L L L L L x H H H H L L L L L x H H H x H H L L H H L L L x H H L L H H L L L x H H L x H L H L H L H L L x H L H L H L H L L x H L H x x x Address Command DESL NOP BST Action Nop or Power down Nop or Power down ILLEGAL 2 2 2 Notes
BA, CA, A10 READ/READA ILLEGAL BA, CA, A10 WRIT/WRITA ILLEGAL BA, RA BA, A10 x Op-Code Op-Code x x x ACT PRE/PALL REF/SELF MRS EMRS DESL NOP BST Bank activating Nop CBR (auto) refresh or Self refresh Mode register set Extended mode register set Nop Nop ILLEGAL
3 4 4 4
2
BA, CA, A10 READ/READA Begin read/read with AP BA, CA, A10 WRIT/WRITA Begin write/write with AP BA, RA BA, A10 x Op-Code Op-Code x x x ACT PRE/PALL REF/SELF MRS EMRS DESL NOP BST ILLEGAL Precharge/Precharge all banks ILLEGAL ILLEGAL ILLEGAL Nop (Row active after burst end) Nop (Row active after burst end) terminate burst, Row active 6 6 2 5
BA, CA, A10 READ/READA terminate burst, Begin new read/ read with AP
L L L
H L L
L H H
L H L
BA, CA, A10 WRIT/WRITA ILLEGAL BA, RA BA, A10 ACT PRE/PALL ILLEGAL terminate burst, Precharge/Precharge all banks 2 6
L L L Write H L L L L
L L L x H H H H
L L L x H H L L
H L L x H L H L
x Op-Code Op-Code x x x
REF/SELF MRS EMRS DESL NOP BST
ILLEGAL ILLEGAL ILLEGAL Nop (Row active after tWR) Nop (Row active after tWR) ILLEGAL
BA, CA, A10 READ/READA terminate burst, Begin read/read with AP 6 BA, CA, A10 WRIT/WRITA terminate burst, Begin new write/ write with AP 6
L L L L L
L L L L L
H H L L L
H L H L L
BA, RA BA, A10 x Op-Code Op-Code
ACT PRE/PALL REF/SELF MRS EMRS
ILLEGAL
2
terminate burst, Precharge/Precharge all 6 banks ILLEGAL ILLEGAL ILLEGAL
Preliminary Data Sheet E0136E30
17
EDD1204ALTA, EDD1208ALTA, EDD1216ALTA
(2/3)
Current state Read with auto precharge /CS /RAS /CAS /WE H L L L L L L L L L Write with auto precharge H L L L L L L L L L Precharge H L L L L L L L L L Row activating H L L L L L L L L L x H H H H L L L L L x H H H H L L L L L x H H H H L L L L L x H H H H L L L L L x H H L L H H L L L x H H L L H H L L L x H H L L H H L L L x H H L L H H L L L x H L H L H L H L L x H L H L H L H L L x H L H L H L H L L x H L H L H L H L L x x x Address Command DESL NOP BST Action Nop (Precharge after burst end) Nop (Precharge after burst end) ILLEGAL Notes
BA, CA, A10 READ/READA ILLEGAL BA, CA, A10 WRIT/WRITA ILLEGAL BA, RA BA, A10 x Op-Code Op-Code x x x ACT PRE/PALL REF/SELF MRS EMRS DESL NOP BST ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Nop (Idle after tDAL) Nop (Idle after tDAL) ILLEGAL 2 2
BA, CA, A10 READ/READA ILLEGAL BA, CA, A10 WRIT/WRITA ILLEGAL BA, RA BA, A10 x Op-Code Op-Code x x x ACT PRE/PALL REF/SELF MRS EMRS DESL NOP BST ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Nop (Idle after tRP) Nop (Idle after tRP) ILLEGAL 2 2 2 2 3 2 2
BA, CA, A10 READ/READA ILLEGAL BA, CA, A10 WRIT/WRITA ILLEGAL BA, RA BA, A10 x Op-Code Op-Code x x x ACT PRE/PALL REF/SELF MRS EMRS DESL NOP BST ILLEGAL Nop (Idle after tRP) ILLEGAL ILLEGAL ILLEGAL Nop (Row active after tRCD) Nop (Row active after tRCD) ILLEGAL
2 2 2 2 2
BA, CA, A10 READ/READA ILLEGAL BA, CA, A10 WRIT/WRITA ILLEGAL BA, RA BA, A10 x Op-Code Op-Code ACT PRE/PALL REF/SELF MRS EMRS ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL
18
Preliminary Data Sheet E0136E30
EDD1204ALTA, EDD1208ALTA, EDD1216ALTA
(3/3)
Current state Write recovering /CS /RAS /CAS /WE H L L L L L L L L L Write recovering with auto precharge H L L L L L L L L L Refresh H L L L L L Mode register accessing H L L L L x H H H H L L L L L x H H H H L L L L L x H H H L L x H H H L x H H L L H H L L L x H H L L H H L L L x H H L H L x H H x x x H L H L H L H L L x H L H L H L H L L x H L x x x x H L x x x x x Address Command DESL NOP BST Action Nop (Row active after tWR) Nop (Row active after tWR) Nop (Row active after tWR) Begin read/read with AP Begin new write/write with AP ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Nop (Idle after tDAL) Nop (Idle after tDAL) ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Nop (Idle after tRFC) Nop (Idle after tRFC) Nop (Idle after tRFC) ILLEGAL ILLEGAL 2 2 3 2 2 2 2 Notes
BA, CA, A10 READ/READA BA, CA, A10 WRIT/WRITA BA, RA BA, A10 x Op-Code Op-Code x x x ACT PRE/PALL REF/SELF MRS EMRS DESL NOP BST
BA, CA, A10 READ/READA BA, CA, A10 WRIT/WRITA BA, RA BA, A10 x Op-Code Op-Code x x x x x x x x x x x ACT PRE/PALL REF/SELF MRS EMRS DESL NOP BST READ/WRIT ACT/PRE/PALL
REF/SELF/MRS/E ILLEGAL MRS DESL NOP BST READ/WRIT Nop (Idle after tMRD) Nop (Idle after tMRD) ILLEGAL ILLEGAL 2 2 2
ACT/PRE/PALL/R ILLEGAL EF/SELF/MRS/EM RS
Remark
H = High level, L = Low level, x = High or Low level (Don't care), BA = Bank address, RA = Row address, CA = Column address, A10 = Precharge control address, Op-Code = Operand code, Nop = No operation, AP = Auto precharge,
ILLEGAL = Device operation and/or data-integrity are not guaranteed Notes 1. All entries assume that CKE is active (High level) during the preceding clock cycle and the current clock cycle. 2. ILLEGAL to bank in specified states; function may be legal in the bank indicated by BA0, BA1 depending on the state of that bank. 3. Nop to bank precharging or in idle state. May precharge bank indicated by BA0, BA1. 4. ILLEGAL if any bank is not idle. 5. ILLEGAL if tRAS is not satisfied. 6. Must satisfy command interval and/or burst terminate condition.
Preliminary Data Sheet E0136E30
19
EDD1204ALTA, EDD1208ALTA, EDD1216ALTA
4.5 Command Truth Table for CKE
Current State CKE n-1 Self refresh H L n x H x H L L Self refresh recovery H H H L Power down H L L H H L x x H x H L x x x H L L All banks idle H H H H H H H L Row active H L Any state except listed above H H L L H L L L L L L x x x H L x x V H L L L L L x x x V x x x x H x x H x x x x H x V x H x H L L x x x V x x x x H x x H x x x x H x V x H x L H L x x x V x x x x x x x H x x x x x x V x H L x x H x x x V x x x x x x x x x x x x x x x x x x x x x x x x V x x SELF PWDN PWDN Maintain power down Refer to operative command table Power down entry Power down entry ILLEGAL ILLEGAL ILLEGAL Self refresh entry Power down Refer to operative command table Power down Refer to operative command table ILLEGAL ILLEGAL (Impossible) 1 1 1 1 PDEX DESL NOP Maintain self refresh Nop (Idle after tRC) Nop (Idle after tRC) ILLEGAL ILLEGAL (Impossible) ILLEGAL (Impossible) Exit power down, Idle SREX ILLEGAL(Impossible) Exit S.R, self refresh recovery 2 /CS /RAS /CAS /WE Add Command Action Notes
Remark H = High level, L = Low level, x = High or Low level (Don't care), V = Valid, Add = Address (A0 - A11, BA0, BA1), ILLEGAL = Device operation and/or data-integrity are not guaranteed Notes 1. Self refresh can be entered only from all banks idle state. Power down can be entered only from all banks idle or row active state. 2. CKE low to high transition will re-enable CLK and other inputs asynchronously. A Minimum setup time must be satisfied before any command other than exit.
20
Preliminary Data Sheet E0136E30
EDD1204ALTA, EDD1208ALTA, EDD1216ALTA
5. Initialization
The EDD12xxALTA is initialized in the power-on sequence according to the following. (1) Power must first be applied to VDD, then VDDQ, and finally to VREF. VTT must be applied. (2) Maintaining an LVCMOS LOW level on CKE during power-up is required to guarantee that the DQ and DQS output will be in Hi-Z state. (3) To stabilize internal circuits, when power is applied a 100 s or longer pause must precede any signal toggling. (4) After the pause, all banks must be precharged using precharge command. The precharge all banks command is convenient. (5) EMRS command must be performed to enable or disable DLL. Then MRS command must be applied to reset DLL. After this MRS command additional 200 cycles are required before read command. (6) All banks must be precharged using precharge command again. Then two or more CBR (auto) refresh command must be performed. (7) After the refresh the mode register can be programmed by MRS command. Case 1: MRS after the REF
Min. 200 cycles before Read command
tMRD
tMRD
tRP
tRFC
tRFC
tMRD
CLK
CKE
Any Command
Command
PALL
EMRS
DLL enable / disable
MRS
DLL reset
PALL
REF
REF
MRS
Minimum 2 REF cycles must be performed.
Remark
Two refresh commands may be follow the first MRS command.
Preliminary Data Sheet E0136E30
21
EDD1204ALTA, EDD1208ALTA, EDD1216ALTA
6. Programming the Mode Register
The mode register is programmed by the Mode register set command using address bits BA0, BA1, A11 through A0 as data inputs. The register retains data until it is reprogrammed or the device loses power. The mode register has five fields; Option DLL reset /CAS latency Wrap type Burst length : A11 through A9, A7 : A8 : A6 through A4 : A3 : A2 through A0
Following mode register programming, no command can be issued during tMRD. /CAS Latency /CAS latency is the critical parameter. It tells how many clocks must elapse before the data is available. The value is determined by the frequency of the clock and the speed grade of the device. Burst Length Burst length is the number of words that will be output or input in read or write cycle. After read burst is completed, the output bus becomes Hi-Z. The burst length is programmable as 2, 4 and 8. Wrap Type (Burst Sequence) The wrap type specifies the order in which the burst data is addressed. This order is programmable as either "Sequential" or "Interleave". The method chosen depends on the type of CPU in the system. Some microprocessor cache system are optimized for sequential addressing and others for interleaved addressing. 7.1 Burst Length and Sequence shows the addressing sequence for each burst length using them. Both sequences support bursts of 2, 4 and 8. The extended mode register has two fields; Option DLL enable : A11 through A1 : A0
22
Preliminary Data Sheet E0136E30
EDD1204ALTA, EDD1208ALTA, EDD1216ALTA
7. Mode Register
BA1 BA0 A11 x x x
A10 x
A9 x
A8 0
A7 1
A6 V
A5 V
A4 V
A3 V
A2 V
A1 V
A0 V
Vender specific
BA1 BA0 A11 0 1 0
A10 0
A9 0
A8 0
A7 0
A6 0
A5 0
A4 0
A3 0
A2 0
A1 0
A0 DLL
Extended mode register set
Bit 0 0 1 DLL Enable Disable
BA1 BA0 A11 0 0 0
A10 0
A9 0
A8 DLL
A7 0
A6
A5 LTMODE
A4
A3 WT
A2
A1 BL
A0
Mode register set
Bit 2 - Bit 0 Bit 8 0 1 DLL Normal Reset Burst Length 000 001 010 011 100
WT = 0 R 2 4 8 R R R R
WT = 1 R 2 4 8 R R R R
Remark V = Valid, x = Don't care
101 110 111
CLK CKE /CS /RAS /CAS /WE A0 - A11, BA0, BA1
Mode register set timming
Wrap Type
Bit 3 0 1
Mode Sequential Interleave
Bit 6 - Bit 4 000 001 Latency Mode 010 011 100 101 110 111
/CAS Latency R R 2 R R R 2.5 R
Remark R: Reserved
Preliminary Data Sheet E0136E30
23
EDD1204ALTA, EDD1208ALTA, EDD1216ALTA
7.1 Burst Length and Sequence
[Burst Length = Two]
Starting Address (column address A0, binary) 0 1 Sequential Addressing Sequence (decimal) 0, 1 1, 0 Interleave Addressing Sequence (decimal) 0, 1 1, 0
[Burst Length = Four]
Starting Address (column address A1 - A0, binary) 00 01 10 11 Sequential Addressing Sequence (decimal) 0, 1, 2, 3 1, 2, 3, 0 2, 3, 0, 1 3, 0, 1, 2 Interleave Addressing Sequence (decimal) 0, 1, 2, 3 1, 0, 3, 2 2, 3, 0, 1 3, 2, 1, 0
[Burst Length = Eight]
Starting Address (column address A2 - A0, binary) 000 001 010 011 100 101 110 111 Sequential Addressing Sequence (decimal) 0, 1, 2, 3, 4, 5, 6, 7 1, 2, 3, 4, 5, 6, 7, 0 2, 3, 4, 5, 6, 7, 0, 1 3, 4, 5, 6, 7, 0, 1, 2 4, 5, 6, 7, 0, 1, 2, 3 5, 6, 7, 0, 1, 2, 3, 4 6, 7, 0, 1, 2, 3, 4, 5 7, 0, 1, 2, 3, 4, 5, 6 Interleave Addressing Sequence (decimal) 0, 1, 2, 3, 4, 5, 6, 7 1, 0, 3, 2, 5, 4, 7, 6 2, 3, 0, 1, 6, 7, 4, 5 3, 2, 1, 0, 7, 6, 5, 4 4, 5, 6, 7, 0, 1, 2, 3 5, 4, 7, 6, 1, 0, 3, 2 6, 7, 4, 5, 2, 3, 0, 1 7, 6, 5, 4, 3, 2, 1, 0
24
Preliminary Data Sheet E0136E30
EDD1204ALTA, EDD1208ALTA, EDD1216ALTA
8. Address Bits of Bank-Select and Precharge
[Activate Command]
BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Row Address
BA1 0 0 1 1
BA0 0 1 0 1
Result Select Bank A, ''Activate'' command Select Bank B, ''Activate'' command Select Bank C, ''Activate'' command Select Bank D, ''Activate'' command
[Precharge Command]
BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Row Address
BA1 0 0 1 1 x
BA0 0 1 0 1 x
A10 0 0 0 0 1
Result Precharge Bank A Precharge Bank B Precharge Bank C Precharge Bank D Precharge All Banks
Remark x = Don't care [Read/Write Command]
BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Column Address
A10 0 1
Result Disables Auto-Precharge Enables Auto-Precharge
BA1 0 0 1 1
BA0 0 1 0 1
Result Enables Read/Write commands for Bank A Enables Read/Write commands for Bank B Enables Read/Write commands for Bank C Enables Read/Write commands for Bank D
Preliminary Data Sheet E0136E30
25
EDD1204ALTA, EDD1208ALTA, EDD1216ALTA
9. Precharge
9.1 Read to Precharge Command Interval The precharge command can be issued anytime after tRAS (MIN.) is satisfied. Soon after the precharge command is issued, precharge operation performed and the DDR SDRAM enters the idle state after tRP is satisfied. The parameter tRP is the time required to perform the precharge. The earliest timing in a read cycle that a precharge command can be issued without losing any data in the burst is as follows. /CAS latency = 2 /CAS latency = 2.5 : (burst length/2) clocks after the read command is issued. : (burst length/2) clocks after the read command is issued.
Burst length = 4 T0 T1 T2 T3 T4 T5
CLK /CLK CKE /CAS latency = 2 Command DQS READ PRE Hi-Z Hi-Z
DQ
Q1
Q2
Q3
Q4
/CAS latency = 2.5 Command DQS READ PRE Hi-Z Hi-Z
DQ
Q1
Q2
Q3
Q4
(Must satisfy tRAS)
26
Preliminary Data Sheet E0136E30
EDD1204ALTA, EDD1208ALTA, EDD1216ALTA
9.2 Write to Precharge Command Interval In order to write all burst data to the memory cell correctly, the asynchronous parameter tWR must be satisfied. The tWR specification defines the earliest time that a precharge command can be issued.
Burst length = 4 T0 T1 T2 T3 T4 tWR CLK /CLK DM /CAS latency = 2, 2.5 Command WRITE Preamble DQS PRE T5
Postamble
Hi-Z DQ Q1 Q2 Q3 Q4
(Must satisfy tRAS)
Preliminary Data Sheet E0136E30
27
EDD1204ALTA, EDD1208ALTA, EDD1216ALTA
10. Auto Precharge
During a read or write command cycle, A10 controls auto precharge. A10 high in the read or write command (read with auto precharge command or write with auto precharge command), auto precharge is selected and begin automatically. The tRAS must be satisfied with a read with auto precharge or a write with auto precharge operation. In addition, the next activate command to the bank being precharged cannot be executed until the precharge cycle ends. In read cycle, once auto precharge starts, an activate command to the bank can be issued after tRP is satisfied. In write cycle, tDAL must be satisfied to issue the next activate command to the bank being precharged.
10.1 Read with Auto Precharge When a read with auto precharge command is issued, the auto precharge begins (Burst length / 2) clocks later from a read with auto precharge command.
Burst length = 4 T0 T1 Burst length / 2 cycle CLK /CLK CKE /CAS latency = 2 Command READA Auto precharge starts ACT T2 T3 tRP T4 T5
Hi-Z DQ Q1 Q2 Q3 Q4
/CAS latency = 2.5 Command READA Auto precharge starts ACT
Hi-Z DQ Q1 Q2 Q3 Q4
(When tRAS is satisfied)
Remark READA means Read with Auto Precharge command
28
Preliminary Data Sheet E0136E30
EDD1204ALTA, EDD1208ALTA, EDD1216ALTA
10.2 Write with Auto Precharge
When a write with auto precharge command is issued, the auto precharge begins after tWR is satisfied.
Burst length = 2 T0 T1 T2 T3 T4 T5 T6
tWR CLK /CLK CKE /CAS latency = 2, 2.5 Command DQS WRITEA Auto precharge starts
tRP
ACT
DQ
D1
D2 (When tRAS is satisfied)
Remark WRITEA means Write with Auto Precharge command
Preliminary Data Sheet E0136E30
29
EDD1204ALTA, EDD1208ALTA, EDD1216ALTA
11. Read/Write Command Interval
11.1 Read to Read Command Interval During a read cycle, when new read command is issued, it will be effective after /CAS latency, even if the previous read operation is not completed. READ will be interrupted by another READ. The interval between commands is minimum 1 cycle. Each read command can be issued in every clock without any restriction.
Burst length = 4 T0 1 cycle CLK /CLK CKE /CAS latency = 2 Command READ A READ B T1 T2 T3 T4 T5 T6
Hi-Z DQ QA1 QA2 QB1 QB2 QB3 QB4
/CAS latency = 2.5 Command READ A READ B
DQ
QA1
QA2
QB1
QB2
QB3
QB4
Hi-Z
30
Preliminary Data Sheet E0136E30
EDD1204ALTA, EDD1208ALTA, EDD1216ALTA
11.2 Write to Write Command Interval During a write cycle, when new write command is issued, the previous burst will terminate and the new burst will begin with new write command. WRITE will be interrupted by another WRITE. The interval between commands is minimum 1 cycle. Each write command can be issued in every clock without any restriction.
Burst length = 4 T0 1 cycle CLK /CLK CKE /CAS latency = 2, 2.5 Command WRITE A WRITE B T1 T2 T3 T4 T5
DQS
DQ
DA1
DA2
DB1
DB2
DB3
DB4
Preliminary Data Sheet E0136E30
31
EDD1204ALTA, EDD1208ALTA, EDD1216ALTA
11.3 Write to Read Command Interval The burst write operation can be interrupted by read command of any bank. The data bus must be high impedance at least 1 cycle prior to the first output data. The minimum time interval between the rising clock edge after the last input data and the read command is tWTR. When the read command is issued, the invalid data from the burst write cycle must be masked by DM.
T0 T1 T2 tWTR CLK /CLK CKE /CAS latency = 2 Command WRITE A READ B T3 T4 T5 T6
DQS
Hi-Z
DQ
DA1
DA2
Hi-Z
QB1
QB2
QB3
QB4
DM
/CAS latency = 2.5 Command WRITE A READ B
DQS
Hi-Z
DQ
DA1
DA2
Hi-Z
QB1
QB2
QB3
DM
DQ and DQS : Input
DQ and DQS : Output
32
Preliminary Data Sheet E0136E30
EDD1204ALTA, EDD1208ALTA, EDD1216ALTA
11.4 Read to Write Command Interval To interrupt the burst read operation using the write command, the burst stop command must be issued to avoid data conflict. The data bus must be high impedance when the write command is issued. When the write command is issued, any residual data from the burst read cycle must be terminated by the burst stop command. When /CAS latency is 2, 2.5, the burst stop command must be issued at least 2 cycles prior to the write command.
T0 T1 T2 T0 T3 T4 T1 T5 T6 T2 T7 T8 T3 T9 T10 T4 T11 T12 T5 T13 T14Burst length = 8 T6
CLK /CLK CKE /CAS latency = 2 Command READ A BST WRITE B
DQS
Hi-Z
DQ
QA1
QA2
QA3
QA4
Hi-Z
DB1
DB2
DB
/CAS latency = 2.5 Command READ A BST WRITE B
DQS
Hi-Z
DQ
QA1
QA2
QA3
QA4
Hi-Z
DB1
DB2
DB
DQ and DQS : Output
DQ and DQS : Input
Preliminary Data Sheet E0136E30
33
EDD1204ALTA, EDD1208ALTA, EDD1216ALTA
12. Burst Termination
12.1 Burst Stop Command in Read Cycle During a burst read cycle, when the burst stop command is issued at the rising edge of the clock (CLK), the burst read data are terminated and the data bus goes to high impedance after the /CAS latency from the burst stop command.
T0 T1 T2 T0 T3 T4 T1 T5 T6 T2 T7 T8 T3 T9 T10 T11 T4 Burst length = 8 T5
CLK /CLK CKE /CAS latency = 2 Command READ BST
Hi-Z DQ Q1 Q2 Q3 Q4
/CAS latency = 2.5 Command READ BST
Hi-Z DQ Q1 Q2 Q3 Q4
(When tRAS is satisfied)
Remark BST means Burst Stop command
34
Preliminary Data Sheet E0136E30
EDD1204ALTA, EDD1208ALTA, EDD1216ALTA
12.2 Terminating a Burst Read Cycle by Precharge Command During a burst read cycle without auto precharge, the burst read operation is terminated by a precharge command of the same banks. When the precharge command is issued at the rising edge of the clock (CLK), the burst read operation is terminated and the data bus goes to high impedance after the /CAS latency from the precharge command. The precharge command can be issued after tRAS (MIN.) is satisfied.
Burst length = Full page T0 T1 T2 T3 T4 T5
CLK /CLK CKE /CAS latency = 2 Command READ PRE
Hi-Z DQ Q1 Q2 Q3 Q4
/CAS latency = 2.5 Command READ PRE
Hi-Z DQ Q1 Q2 Q3 Q4
(When tRAS is satisfied)
Preliminary Data Sheet E0136E30
35
EDD1204ALTA, EDD1208ALTA, EDD1216ALTA
12.3 Terminating a Burst Write Cycle by Precharge Command During a burst write cycle without auto precharge, the burst write operation is terminated by a precharge command of the same banks. In order to write the last input data to the memory cell correctly, tWR (MIN.) must be satisfied. When the precharge command is issued at the rising edge of the clock (CLK), the invalid data from the burst write cycle must be masked by DM.
Burst length = 8 T0 T1 T2 T3 tWR CLK /CLK CKE /CAS latency = 2, 2.5 Command WRITE PRE T4 T5
DQS
DQ
D1
D2
DM
36
Preliminary Data Sheet E0136E30
EDD1204ALTA, EDD1208ALTA, EDD1216ALTA
13. Electrical Specifications
* All voltages are referenced to VSS (GND). * After power up, wait more than 100 s and then, execute Power on sequence and CBR (auto) Refresh before proper device operation is achieved. 13.1 Absolute Maximum Ratings
Parameter Voltage on power supply pin relative to VSS Voltage on any pin relative to VSS Short circuit output current Power dissipation Storage temperature Symbol VDD, VDDQ VT IO PD Tstg Condition Rating -0.5 to +3.6 -0.5 to +3.6 50 1 -55 to + 125 Unit V V mA W C
Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability.
13.2 Recommended Operating Conditions
Parameter Supply voltage Supply voltage for DQ, DQS Input reference voltage Termination voltage High level dc input voltage Low level dc input voltage Input differential voltage (CLK and /CLK) Input crossing point voltage (CLK and /CLK) Operating ambient temperature Symbol VDD VDDQ VREF VTT VIH (DC) VIL (DC) VID (DC) VIX TA Condition MIN. 2.3 2.3 0.49 x VDDQ VREF - 0.04 VREF + 0.18 -0.3 0.36 0.5 x VDDQ-0.2 0 VREF TYP. 2.5 2.5 MAX. 2.7 2.7 0.51 x VDDQ VREF + 0.04 VDD + 0.3 VREF - 0.18 VDDQ + 0.6 0.5 x VDDQ+0.2 70 Unit V V V V V V V V C
13.3 Pin Capacitance (TA = 25 C, f = 100 MHz)
Parameter Input capacitance Symbol CI1 CI2 Data input/output capacitance CIO1 CIO2 Condition A0 - A11, BA0, BA1 CLK, /CLK, CKE, /CS, /RAS, /CAS, /WE DQS, LDQS, UDQS DQ0 - DQ15, DM, LDM, UDM MIN. 2.5 2.5 4 4 TYP. MAX. 3.5 3.5 5 5 Unit pF pF pF pF
Preliminary Data Sheet E0136E30
37
EDD1204ALTA, EDD1208ALTA, EDD1216ALTA
13.4 DC Characteristics 1 (Recommended Operating Conditions unless otherwise noted)
Parameter Symbol Test condition /CAS Grade latency -7A Maximum x4 x8 115 x16 mA 1 Unit Notes
Operating current (ACT-PRE)
IDD0
tRC = tRC(MIN.), tCK = tCK (MIN.), One bank, Active-precharge, DQ, DM and DQS inputs changing twice per clock cycle, Address and control inputs changing once per clock cycle
-75
115
-1A
100
Operating current (ACT-READ-PRE)
IDD1
tRC = tRC(MIN.), tCK = tCK (MIN.), One CL = 2 bank, Active-read-precharge, IO = 0 mA, Burst length = 2, Address and control inputs changing once per clock cycle CL = 2.5
-7A -75 -1A -7A -75 -1A
140 130 130 150 150 140
150 140 140 160 160 150 2 45
170 160 160 180 180 170
mA
Precharge power down standby current Idle standby current
IDD2P IDD2N
CKE VIL(MAX.), tCK = tCK(MIN.), All banks idle, Power down mode CKE VIH(MIN.), tCK = tCK(MIN.), /CS VIH(MIN.), All banks idle, Address and other control inputs changing once per clock cycle CKE VIL(MAX.), tCK = tCK(MIN.), One bank active, Power down mode /CS VIH(MIN.), CKE VIH(MIN.), tCK = tCK(MIN.), tRC = tRAS(MAX.), One bank, Active-precharge, DQ, DM and DQS inputs changing twice per clock cycle, Address and other control inputs changing once per clock cycle tCK = tCK(MIN.), Continuous burst read, Burst length = 2, IO = 0mA, One bank active, Address and control inputs changing once per clock cycle CL = 2 -7A -75 -1A CL = 2.5 -7A -75 -1A 200 170 170 210 210 180 195 160 160 195 195 160
mA mA
Active power down standby current Active standby current
IDD3P IDD3N
25 65
mA mA
Operating current (Burst read)
IDD4R
210 180 180 220 220 190 205 170 170 205 205 170 250 250 220 2
230 200 200 240 240 210 225 190 190 225 225 190
mA
2
Operating current (Burst write)
IDD4W
tCK = tCK(MIN.), Continuous burst write, Burst length = 2, One bank active, Address and control inputs changing once per clock cycle
CL = 2
-7A -75 -1A
mA
2
CL = 2.5
-7A -75 -1A
CBR (auto) refresh current
IDD5
tRFC = tRFC(MIN.)
-7A -75 -1A
mA
Self refresh current
IDD6
CKE 0.2 V
mA
Notes 1. IDD1 depends on output loading and cycle rates. Specified values are obtained with the output open. 2. IDD4R and IDD4W depend on output loading and cycle rates. Specified values are obtained with the output open.
38
Preliminary Data Sheet E0136E30
EDD1204ALTA, EDD1208ALTA, EDD1216ALTA
13.5 DC Characteristics 2 (Recommended Operating Conditions unless otherwise noted)
Parameter Input leakage current Output leakage current Output high current Output low current Symbol II(L) IO(L) IOH IOL Test condition Any input 0 V VIN VDD, all other pins not under test = 0 V DOUT is disabled, VO = 0 to VDDQ + 0.3 V VOUT = 1.95 V VOUT = 0.35 V MIN. -2 -5 -15.2 15.2 MAX. 2 5 Unit Notes
A A
mA mA
13.6 AC Characteristics (Recommended Operating Conditions unless otherwise noted) 13.6.1 Test Conditions
Parameter Input Reference voltage (Input timing measurement reference level) Termination voltage (Output timing measurement reference level) High level ac input voltage Low level ac input voltage Input differential voltage (CLK and /CLK) Input signal slew rate Symbol VREF VTT VIH(ac) VIL(ac) VID(ac) SLEW 0.7 1 MIN. 0.49 x VDDQ VREF - 0.04 VREF + 0.31 VREF - 0.31 VDDQ + 0.6 MAX. 0.51 x VDDQ VREF + 0.04 Unit V V V V V V/ns 2 1 Notes
Notes 1. Output waveform timing is measured where the output signal crosses through the VTT level. 2. Slew rate is to be maintained in the VIL (ac) to VIH(ac) range of the input signal swing. SLEW = (VIH(ac)-VIL(ac))/ t
VTT RT = 50 Output CLOAD = 30 pF
Preliminary Data Sheet E0136E30
39
EDD1204ALTA, EDD1208ALTA, EDD1216ALTA
13.6.2 Timing Diagram
tCK CLK
VID(ac)
tCH
tCL
/CLK tIS Command (Input)
VREF + 0.31 V
tIH
tIS
tIH
Valid
VREF - 0.31 V
Valid
tIS Address (Input)
VREF + 0.31 V
tIH
tIS
tIH
Valid
VREF - 0.31 V
Valid
tRPRE
tDQSCK
tRPST tDQSCK
DQS (Output) (CL = 2)
VTT tQH tDQSQ tAC tQH tDQSQ tAC Valid
DQ (Output) (CL = 2)
VTT
Valid
tRPRE tDQSCK DQS (Output) (CL = 2.5)
tRPST tDQSCK
VTT tQH tDQSQ tAC tQH tDQSQ tAC Valid
DQ (Output) (CL = 2.5)
VTT
Valid
tDQSS (MIN.) DQS (Input)
tDQSH tDQSS
VREF + 0.31 V
tDQSL
tDSH
VREF
VREF - 0.31 V tWPRES tWPRE VREF + 0.31 V
tWPST
DQ and DM (Input)
VREF VREF - 0.31 V
Valid
Valid
tDS tDH tDQSS (MAX.) DQS (Input) tDQSS
VREF + 0.31 V
tDS tDH tDQSH tDSS tDQSL
VREF
VREF - 0.31 V tWPRES tWPRE VREF + 0.31 V
tWPST
DQ and DM (Input)
VREF VREF - 0.31 V
Valid
Valid
tDS tDH
tDS tDH
40
Preliminary Data Sheet E0136E30
EDD1204ALTA, EDD1208ALTA, EDD1216ALTA
13.6.3 Synchronous Characteristics
Parameter Symbol MIN. Clock cycle time CL = 2.5 CL = 2 CLK high-level width CLK low-level width DQ output access time from CLK, /CLK DQS output access time from CLK, /CLK DQS-DQ skew (for DQS and associated DQ signals) DQS-DQ skew (for DQS and all DQ signals) Data out low-impedance time from CLK, /CLK Data out high-impedance time from CLK, /CLK Half clock period Read preamble Read postamble DQ output hold time from DQS DQ and DM input setup time DQ and DM input hold time DQ and DM input pulse width (for each input) Write preamble setup time Write preamble Write postamble Write command to first DQS latching transition DQS input high pulse width DQS input low pulse width DQS falling edge to CLK setup time DQS falling edge hold time from CLK Address and control input setup time Address and control input hold time Address and control input pulse width Internal write to read command delay tCH tCL tAC tDQSCK tDQSQ tDQSQA tLZ tHZ tHP tRPRE tRPST tQH tDS tDH tDIPW tWPRES tWPRE tWPST tDQSS tDQSH tDQSL tDSS tDSH tIS tIH tIPW tWTR -0.75 -0.75 MIN. (tCH, tCL) 0.9 0.4 tHP - 0.75 0.5 0.5 1.75 0 0.25 0.4 0.75 0.35 0.35 0.2 0.2 0.9 0.9 2.2 1 0.6 1.25 1.1 0.6 tCK 7.5 7.5 0.45 0.45 -0.75 -0.75 -7A MAX. 12 12 0.55 0.55 0.75 0.75 0.5 0.5 0.75 0.75 -0.75 -0.75 MIN. (tCH, tCL) 0.9 0.4 tHP - 0.75 0.5 0.5 1.75 0 0.25 0.4 0.75 0.35 0.35 0.2 0.2 0.9 0.9 2.2 1 0.6 1.25 1.1 0.6 MIN. 7.5 10 0.45 0.45 -0.75 -0.75 -75 MAX. 12 12 0.55 0.55 0.75 0.75 0.5 0.5 0.75 0.75 -0.8 -0.8 MIN. (tCH, tCL) 0.9 0.4 tHP - 1 0.6 0.6 2 0 0.25 0.4 0.75 0.35 0.35 0.2 0.2 1.1 1.1 2.5 1 0.6 1.25 1.1 0.6 MIN. 10 10 0.45 0.45 -0.8 -0.8 1A MAX. 12 12 0.55 0.55 0.8 0.8 0.6 0.6 0.8 0.8 tCK tCK ns ns ns ns ns ns ns tCK tCK ns ns ns ns ns tCK tCK tCK tCK tCK tCK tCK ns ns ns tCK ns Unit Note
Preliminary Data Sheet E0136E30
41
EDD1204ALTA, EDD1208ALTA, EDD1216ALTA
13.6.4 Synchronous Characteristics Example
Symbol tCK =7.5 ns MIN. tCH tCL tRPRE tRPST tWPRE tWPST tDQSS tDQSH tDQSL tDSS tDSH tWTR 3.4 3.4 6.75 3 1.88 3 5.6 2.63 2.63 1.5 1.5 7.5 4.5 9.4 MAX. 4.1 4.1 8.25 4.5 tCK =10 ns MIN. 4.5 4.5 9 4 2.5 4 7.5 3.5 3.5 2 2 10 6 12.5 MAX. 5.5 5.5 11 6 ns ns ns ns ns ns ns ns ns ns ns ns Unit
13.6.5 Asynchronous Characteristics
Parameter Symbol MIN. ACT to REF/ACT command period (operation) REF to REF/ACT command period (refresh) ACT to PRE command period PRE to ACT command period ACT to READ/WRITE delay ACT(one) to ACT(another) command period Write recovery time Auto precharge write recovery time + precharge time Mode register set command cycle time Exit self refresh to command Average periodic Refresh interval tMRD tXSNR tREF1 15 75 15.6 15 75 15.6 15 80 15.6 ns ns s tRFC tRAS tRP tRCD tRRD tWR tDAL 75 45 20 20 15 2 35 120,000 75 45 20 20 15 2 35 120,000 80 50 20 20 15 2 35 120,000 ns ns ns ns ns CLK ns tRC 65 -7A MAX. MIN. 65 -75 MAX. MIN. 70 -1A MAX. ns Unit
42
Preliminary Data Sheet E0136E30
AC Parameters for Read Timing 1 (Manual Precharge, Burst Length = 4, /CAS Latency = 2.5)
T0 tCK CLK tCH tCK /CLK tCL CKE tIS tCH tCL T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13
;; ;; ;; ; ;; ;; ; ;;; ;; ;; ;; ;; ; ;;; ;; ;; ;; ;; ; ;;; ;; ;; ;; ;;; ;; ;; ;; ; ;; ; ;; ; ;; ;;; ;; ;; ;; ; ; ;;; ;; ;; ;; ;;; ;; ;; ;; ;; ; ;; ; ;; ;;; ;; ; ;; ; ;; ;; ;; ; ;;; ;; ; ;; ; ; ; ;; ;; ;;; ;; ; ;; ; ;; ; ;; ;;; ;; ;; ;; ; ;; ;;; ;; ;; ;; ;; ;;; ;; ;; ;; ;; ;;; ;; ;; ; ;; ;;; ;; ;; ;; ; ;; ;;; ;; ;;; ;; ;; ; ;;
tIH
tIS tIH /CS /RAS /CAS
BA0
BA1
A10
ADD
tIS tIH
DM
L
tRPRE
DQS
VTT
Hi-Z
DQ
VTT
Hi-Z
tRCD
tRAS
tRC
Activate Command for Bank A Read Command for Bank A Precharge Command for Bank A Activate Command for Bank A
;; ;; ;; ;;
tDQSCK tDQSCK tDQSCK tDQSCK tRPST tDQSQ tDQSQ tDQSQ tDQSQ tQH tQH tQH tAC tQH tAC tAC tAC
Preliminary Data Sheet E0136E30
EDD1204ALTA, EDD1208ALTA, EDD1216ALTA
/WE
tRP
43
BA1
A10
ADD
tIS tIH
DM
DQS
VTT
Hi-Z
DQ
VTT
Hi-Z
tRCD
Activate Command for Bank C
;; ;; ;; ;;
tDQSCK tDQSCK tDQSCK tDQSCK tRPRE tRPST tDQSQ tDQSQ tDQSQ tDQSQ tQH tQH tQH tQH
44
Preliminary Data Sheet E0136E30
AC Parameters for Read Timing 2 (Auto Precharge, Burst Length = 4, /CAS Latency = 2.5)
T0 tCK CLK tCH tCL
tCK
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
;;; ; ;; ;; ;; ;;;; ; ;; ;;; ;; ;; ;;;; ; ;; ;;; ;; ;; ;;;; ; ;; ;;; ;; ;; ;; ;; ;; ;; ;;;;; ;; ;; ;; ; ; ;;;;; ;; ;; ; ;; ; ;;;;;; ;; ;; ; ;; ;; ; ;; ;; ;;;;;; ;; ;; ; ;; ; ;;; ; ;; ;; ;; ; ; ;; ;;; ; ; ;; ; ; ; ;; ;;; ; ; ;; ; ; ; ;; ;;; ;; ;; ;; ; ;; ;; ;;;; ;; ; ;; ; ;; ;;;; ;; ;; ;; ; ;; ;;;; ;; ;; ;; ; ; ;; ;;;; ;; ; ;; ;; ;; ;;;;; ;;;; ;; ;; ;; ;; ;
/CLK tCL tCH
CKE
tIS
tIS
tIH
Auto Precharge Start for Bank C
tIH
/CS
/RAS
/CAS /WE
EDD1204ALTA, EDD1208ALTA, EDD1216ALTA
BA0
tRAS
tAC
tAC
tAC
tAC
tRRD
tRC
Bank C Read Command with Auto Precharge
Activate Command for Bank D
Activate Command for Bank C
EDD1204ALTA, EDD1208ALTA, EDD1216ALTA
Relationship between Frequency and Latency
Speed version Clock cycle time [ns] Frequency [MHz] /CAS latency [tRCD] /RAS latency (/CAS latency + [tRCD]) [tRC] [tRFC] [tRAS] [tRRD] [tRP] [tWR] [tDAL] [tMRD] [tXSNR] 7.5 133 2.5 3 5.5 9 10 6 2 3 2 5 2 10 -7A 7.5 133 2 3 5 9 10 6 2 3 2 5 2 10 7.5 133 2.5 3 5.5 9 10 6 2 3 2 5 2 10 -75 10 100 2 2 4 7 8 5 2 2 2 4 2 8 10 100 2.5 2 4.5 7 8 5 2 2 2 4 2 8 -1A 10 100 2 2 4 7 8 5 2 2 2 4 2 8
Preliminary Data Sheet E0136E30
45
46
Preliminary Data Sheet E0136E30
AC Parameters for Write Timing (Burst Length = 8, /CAS Latency = 2.5)
T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21
/CLK
CKE /CS
tIS tIS tIH
Auto Precharge Start for Bank C
tIH
/RAS
/CAS
EDD1204ALTA, EDD1208ALTA, EDD1216ALTA
/WE
BA0 BA1
A10
ADD tIS tIH DM
tWPRES tDQSS tWPRE
DQS
VTT
Hi-Z tDS
tWPST
tDH
DQ
VTT
Hi-Z tRCD tRC tRRD tRCD tRAS tRC Bank C Activate Activate Write Command Command Command for Bank C with Auto Precharge for Bank B tWR tRP tDAL
Bank B Write Command without Auto Precharge
Activate Command for Bank C
Precharge Command for Bank B
Activate Command for Bank B
;; ;; ;; ; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ; ;;
EDD1204ALTA, EDD1208ALTA, EDD1216ALTA
tMRD ADDRESS KEY Mode Register Set Command Hi-Z VTT DQS ADD BA0 BA1 A10 DM DQ VTT Hi-Z All Banks Precharge Command /CAS /WE
Preliminary Data Sheet E0136E30
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
Mode Register Set (Burst Length = 4, /CAS Latency = 2)
T3
T4
T5
Activate Command is valid tRP
T0
T1
T2
T6
H
/RAS CKE
CLK
/CLK
/CS
47
48
Preliminary Data Sheet E0136E30
Power On Sequence and CBR (auto) Refresh
T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
/CLK
CKE Low level is necessary /CS tMRD 2 refresh cycles are necessary
/RAS
/CAS
/WE
BA0
BA1
A10
ADD
DM
DQS DQ
;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;;; ; ;; ;; ;; ;; ;; ;; ;; ;;; ; ;;; ; ; ;; ;;; ;; ; ;; ;; ;;; ; ; ;; ;; ; ;; ;; ;; ;;; ; ;; ; ;; ;; ;;; ; ;; ; ;; ;; ;;; ; ;; ;; ;; ;; ;; ; ;; ;; ;; ;;; ; ;; ; ;; ;; ;;; ; ;; ; ;; ;; ;; ;; ;;; ; ;; ; ;; ;; ;;; ; ;; ;; ;; ;; ;;; ; ;; ;; ;; ;;; ; ;;; ; ;;;; ;;; ;; ;;; ; ;;; ; ;; ; ;; ;;; ;; ;; ;;; ; ; ;; ;;; ; ;;;; ;; ; ;;; ;;; ; ;;;; ;; ; ;; ;; ;; ;;; ; ; ;; ;;; ; ;;;; ;;; ; ;;; ;;; ;; ;
EDD1204ALTA, EDD1208ALTA, EDD1216ALTA
ADDRESS KEY ADDRESS KEY ADDRESS KEY VTT Hi-Z Hi-Z VTT All Banks Precharge Command is necessary All Banks Extended Mode Mode Refresh Precharge Register Set Register Set Command Command Command Command is necessary is necessary (DLL enable / (DLL reset) disable) is necessary is necessary tMRD tMRD tRP Refresh Command is necessary Mode Register Set Command is necessary Activate Command tRFC tRFC
More than 200 cycles are necessary before Read command
/CS Function (at 100 MHz, Burst Length = 4, /CAS Latency = 2.5) Only /CS signal needs to be issued at minimum rate
T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21
/CLK
CKE
H
/CS
/RAS
Preliminary Data Sheet E0136E30
EDD1204ALTA, EDD1208ALTA, EDD1216ALTA
/CAS
/WE
BA0
L
BA1
L
A10
RAa
ADD
RAa
CAa
CAb
DM
L Hi-Z
DQS VTT
Hi-Z DQ VTT
QAa1 QAa2 QAa3 QAa4
DAb1 DAb2 DAb3 DAb4
Activate Command for Bank A
Read Command for Bank A
Write Command for Bank A
Precharge Command for Bank A
49
50
Preliminary Data Sheet E0136E30
Power Down Mode (Burst Length = 4, /CAS Latency = 2)
T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21
/CLK tIS CKE
;; ;; ; ;; ; ;;; ; ; ;; ; ; ;;; ; ; ;; ; ; ;;; ; ; ;; ; ; ;;; ; ; ;; ; ; ;; ; ;;; ; ;; ; ; ;; ;;; ; ;; ;; ;; ; ;;; ; ;; ; ;; ;;; ; ;; ;; ; ; ; ;; ;;; ; ;; ;; ; ; ;; ;;; ; ;; ;; ; ; ;; ;;; ; ;; ;; ; ; ;; ;;; ; ;; ;; ; ; ;; ;;; ; ;; ;; ; ; ;; ;;; ; ;; ;; ; ; ;;; ; ; ;; ;;; ;; ;; ;; ;; ;; ;; ; ;;; ; ;; ;; ; ; ;
/CS /RAS /CAS
EDD1204ALTA, EDD1208ALTA, EDD1216ALTA
/WE
BA0
BA1
A10
RAa
ADD DM
RAa
CAa
DQS VTT VTT
Hi-Z
Hi-Z
DQ
QAa1 QAa2 QAa3 QAa4
Precharge Command for Bank A Power Down Mode Entry PRECHARGE STANDBY
Activate Command for Bank A Power Down Mode Exit
Read Command for Bank A
;; ;;; ; ;; ;; ;; ;;; ; ; ;; ;;; ;; ;; ;;; ; ;; ;; ; ;; ;; ;;; ; ; ; ; ;; ;; ;; ;;; ; ;;; ;; ;; ;; ;; ;; ;; ;; ;;; ; ;; ; ;; ;; ;;; ;; ;; ;;; ; ; ;; ;;; ;; ;; ;;; ; ; ;; ;;; ;; ;; ;;; ; ; ;; ;; ;;; ; ;; ;; ;; ;; ;; ; ;; ;; ;; ;;; ; ; ;; ;; ;; ;;; ;; ;; ;;; ; ; ;; ;;; ;; ;; ;;; ; ; ;; ;;; ;; ;; ;;; ; ; ;; ;;; ; ;; ; ;; ;; ;; ;; ;; ;; ; ;; ;; ;; ;; ;;; ; ; ;; ; ;; ;; ;;; ; ;; ;; ;; ;; ;; ;; ;; ;;; ; ; ;; ;;; ;; ;; ;;; ; ; ;; ;;;
EDD1204ALTA, EDD1208ALTA, EDD1216ALTA
Q1 Q2 Activate Command CBR (auto) Refresh Precharge CBR (auto) Refresh Command is necessary VTT Hi-Z /RAS /CAS DQS ADD BA0 BA1 /WE A10 DM DQ VTT Hi-Z
Preliminary Data Sheet E0136E30
T19
T20
T21
T14
T15
T16
T17
T18
Read Command tRP tRFC tRFC
CBR (auto) Refresh
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
/CLK
CKE
CLK
H /CS
51
52
Preliminary Data Sheet E0136E30
Self Refresh (Entry and Exit)
;; ; ;;; ; ;; ;; ; ;; ;; ;; ; ;; ;; ;;; ; ;; ;;; ; ; ;; ; ;; ;; ;;; ; ;; ;; ;;; ; ;; ; ;; ;; ;;; ; ;; ; ;; ;; ;;; ; ;; ;; ; ;;; ; ; ;; ; ;; ;; ;;; ; ; ;; ;; ;;; ; ; ;;;;; ; ;; ;; ; ;;;;; ; ;; ;; ; ;;; ; ; ;; ; ;; ;; ;; ;;; ; ;; ; ;;; ; ;; ; ; ; ;;; ; ;; ; ;; ;;
T0 T1 T2 T3 T4 Tn Tn+1 Tn+2 Tm Tm+1 Tm+2 Tk Tj Tj+1 Tj+2 CLK /CLK CKE /CS /RAS /CAS
EDD1204ALTA, EDD1208ALTA, EDD1216ALTA
/WE
BA0
BA1
A10
ADD
DM
Hi-Z DQS VTT Hi-Z DQ VTT
Precharge Command is necessary tRP
Self Refresh Entry
Self Refresh Exit
Self Refresh Self Refresh Entry Exit (or Activate Command) tXSNR Next Clock Enable tXSNR
Activate Command Next Clock Enable
Random Column Read (Page with Same Bank) (1/2) (Burst Length = 4, /CAS Latency = 2)
T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21
;; ; ;; ;;; ; ;; ; ;;; ;; ;;;; ; ;; ; ;;; ;; ;;;; ; ;; ; ;;; ;; ;;;; ; ;; ; ;;; ;; ;;;; ; ;; ;; ; ;; ;;;; ; ;; ; ;;; ;;;; ; ;; ;; ;;; ; ; ;; ;;;; ; ;;; ;; ; ;; ;; ; ;; ;;;; ; ;; ; ;; ;; ;; ;; ;;; ; ;; ;; ;;;; ; ;; ;; ;; ;; ;; ;;;; ; ;; ;; ;; ;; ;; ;;;; ; ;;; ;; ; ;; ;; ;; ; ;;;; ; ;; ;;; ;; ; ;; ;; ; ;;;; ; ;; ;; ; ;; ;;; ;; ;; ;; ; ;; ;; ;;;; ; ;; ;; ; ;; ;; ;; ; ;;;; ; ;; ; ;;;; ; ;; ;; ;; ;; ; ;;;; ; ;; ; ;; ;; ;; ;;;
/CLK CKE H /CS /RAS
Preliminary Data Sheet E0136E30
EDD1204ALTA, EDD1208ALTA, EDD1216ALTA
/CAS
/WE
BA0
BA1
A10
RAa
RAd
ADD
RAa
CAa
CAb
CAc
RAd
CAd
DM
DQS
VTT
Hi-Z
DQ
VTT
Hi-Z
QAa1 QAa2 QAa3 QAa4 QAb1 QAb2 QAc1 QAc2 QAc3 QAc4
QAd1 QAd2 QAd3 QAd4
Activate Command for Bank A
Read Command for Bank A
Read Read Command Command for Bank A for Bank A
Precharge Command for Bank A
Activate Command for Bank A
Read Command for Bank A
53
54
Preliminary Data Sheet E0136E30
Random Column Read (Page with Same Bank) (2/2) (Burst Length = 4, /CAS Latency = 2.5)
T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21
; ; ;;; ;; ; ;; ; ;; ;;;; ;; ; ;; ; ;; ;;;; ;; ; ;; ; ;; ;;;; ;; ; ;; ; ;; ;;;; ;; ;; ;; ; ; ; ;; ;;;; ;; ; ;; ; ;; ;;;; ;; ; ; ;; ; ;; ; ;; ; ;; ;;;; ;; ;; ; ;; ;;;; ;; ; ;; ;; ;; ;; ; ;; ;; ;; ; ;; ;;;; ;; ;;; ; ; ;; ;; ;; ; ;;;; ;; ;; ;;; ; ; ;; ;; ; ;;;; ;; ;; ;; ;; ; ; ;; ; ;;;; ;; ; ;; ;; ; ;; ;; ; ;;;; ;; ; ;; ;; ; ;; ;; ; ;;;; ;; ; ;; ; ;;;; ;; ;; ;; ; ;; ;;;; ;; ;; ; ;; ;; ;; ;;
/CLK CKE H /CS /RAS
EDD1204ALTA, EDD1208ALTA, EDD1216ALTA
/CAS
/WE
BA0
BA1
A10
RAa
RAa
ADD
RAa
CAa
CAb
CAc
RAa
CAa
DM
DQS
VTT
Hi-Z
DQ
VTT
Hi-Z
QAa1 QAa2 QAa3 QAa4 QAb1 QAb2 QAc1 QAc2 QAc3 QAc4
QAd1 QAd2 QAd3 QAd4
Activate Command for Bank A
Read Command for Bank A
Read Read Command Command for Bank A for Bank A
Precharge Command for Bank A
Activate Command for Bank A
Read Command for Bank A
Random Column Write (Page with Same Bank) (1/2) (Burst Length = 4, /CAS Latency = 2)
T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21
/CLK
CKE
H
/CS
/RAS
/CAS
Preliminary Data Sheet E0136E30
EDD1204ALTA, EDD1208ALTA, EDD1216ALTA
/WE
BA0 BA1
A10
RDa
RDd
ADD
RDa
CDa
CDb
CDc
RDd
CDd
DM
DQS
VTT VTT
Hi-Z Hi-Z
DQ
DDa1 DDa2 DDa3 DDa4 DDb1 DDb2 DDc1 DDc2 DDc3 DDc4
DDd1 DDd2 DDd3 DDd4
Activate Command for Bank D
Write Command for Bank D
Write Command for Bank D Write Command for Bank D
Precharge Command for Bank D
Activate Command for Bank D
Write Command for Bank D
55
56
Preliminary Data Sheet E0136E30
Random Column Write (Page with Same Bank) (2/2) (Burst Length = 4, /CAS Latency = 2.5)
T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21
/CLK
CKE
H
/CS
/RAS
/CAS
EDD1204ALTA, EDD1208ALTA, EDD1216ALTA
/WE
BA0 BA1
A10
RDa
RDd
ADD
RDa
CDa
CDb
CDc
RDd
CDd
DM
L Hi-Z Hi-Z
DQS
VTT VTT
DQ
DDa1 DDa2 DDa3 DDa4 DDb1 DDb2 DDc1 DDc2 DDc3 DDc4
DDd1 DDd2 DDd3 DDd4
Activate Command for Bank D
Write Command for Bank D
Write Command for Bank D Write Command for Bank D
Precharge Command for Bank D
Activate Command for Bank D
Write Command for Bank D
Random Row Read (Ping-Pong Banks) (1/2) (Burst Length = 8, /CAS Latency = 2)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21
CLK
/CLK
;; ; ;; ;;; ;; ;; ; ;; ;;; ;; ;; ;; ; ;; ;;; ;; ;; ;; ; ;; ;;; ;; ;; ;; ; ; ;; ;; ; ;;; ;; ;; ; ;; ;; ; ; ;; ;;; ;; ;; ;; ; ;; ;;; ;; ;; ;; ; ;; ;;; ;; ;; ;; ; ;; ;;; ;; ;; ;; ;; ; ; ;; ;; ;; ; ;; ;;; ;; ;; ;; ;; ;; ;;;; ; ;; ;; ;; ;; ;;;; ; ;; ;; ; ;; ;; ;; ;;; ;; ;; ;; ; ;; ;; ; ; ;; ;;; ;; ;; ; ; ;; ;; ; ;; ;; ; ; ;; ; ;;; ;; ;; ;; ;; ; ;; ; ; ;;; ;; ;; ; ; ;;; ;; ;; ;; ; ;; ;;; ;; ;; ;; ;;; ;;;
CKE H /CS /RAS /CAS
Preliminary Data Sheet E0136E30
EDD1204ALTA, EDD1208ALTA, EDD1216ALTA
/WE
BA0
BA1
A10
RDa
RBa
RDb
ADD
RDa
CDa
RBa
CBa
RDb
CDb
DM
DQS VTT DQ VTT
Hi-Z
Hi-Z QDa1 QDa2 QDa3 QDa4 QDa5 QDa6 QDa7 QDa8 QBa1 QBa2 QBa3 QBa4 QBa5 QBa6 QBa7 QBa8 QDb1 QDb2 QDb3 QDb4 QDb5 QDb6 QDb7 QDb8
Activate Command for Bank D
Read Command for Bank D
Activate Command for Bank B
Read Command for Bank B Precharge Command for Bank D
Activate Command for Bank D
Read Command for Bank D
57
58
Preliminary Data Sheet E0136E30
Random Row Read (Ping-Pong Banks) (2/2) (Burst Length = 8, /CAS Latency = 2.5)
T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21
/CLK
;;; ;; ;; ;;; ; ; ;; ;;;; ;; ;;; ; ; ;;;; ;; ;;; ; ; ; ;;; ;; ;; ;;; ;;; ; ; ;; ; ; ;; ;; ;;;; ; ;; ;;;;;; ;;; ;;; ; ; ;; ; ;; ;;;;;; ;;; ; ;;; ;;;;;; ;; ; ;;; ; ;; ;;; ; ;;;; ; ;;;;; ;;; ;;;; ; ;; ;; ;; ; ;; ;; ;;; ;;;; ;;;;;; ;;;;; ;; ;;; ; ; ;; ;; ;; ;;;;;; ; ;; ;; ;; ;;;;;; ;;; ; ; ;;; ;;;;;; ;;; ; ;;; ;;;;;; ;; ;; ;; ;; ;;;; ; ;;;;; ;;; ;;;; ;;;; ; ;;;;; ;;;;
CKE H /CS /RAS /CAS
EDD1204ALTA, EDD1208ALTA, EDD1216ALTA
/WE
BA0
BA1
A10
RBa
RAa
RBb
ADD
RBa
CBa
RAa
CAa
RBb
CBb
DM
DQS
VTT VTT
Hi-Z
Hi-Z QBa1 QBa2 QBa3 QBa4 QBa5 QBa6 QBa7 QBa8 QAa1 QAa2 QAa3 QAa4 QAa5 QAa6 QAa7 QAa8 QBb1 QBb2 QBb3 QBb4 QBb5 QBb6 QBb7
DQ
Activate Command for Bank B
Read Command for Bank B Activate Command for Bank A
Read Command for Bank A
Precharge Command for Bank B
Activate Command for Bank B
Read Command for Bank B
Precharge Command for Bank A
Random Row Write (Ping-Pong Banks) (1/2) (Burst Length = 8, /CAS Latency = 2)
T0 CLK
/CLK
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
;;; ;; ; ;;; ; ;; ; ;; ;;; ; ;; ; ;; ;;; ; ;; ; ;; ;;; ; ;; ; ;; ;;; ; ;; ; ; ; ;;; ; ;; ; ; ; ;;; ; ;; ; ;; ; ;;; ; ;; ;; ; ;; ; ;; ; ; ;;; ; ;; ;; ; ; ;;; ; ;; ; ; ;;;; ;;; ; ;; ;; ; ; ;;;; ;; ; ; ;; ; ;;; ; ;;; ; ; ;; ;; ;; ; ; ; ; ; ;;; ; ;; ; ; ;; ; ; ;;; ; ;; ; ; ;; ; ;; ; ;; ;; ; ; ;;; ; ;; ; ;; ;
CKE H /CS /RAS /CAS
Preliminary Data Sheet E0136E30
EDD1204ALTA, EDD1208ALTA, EDD1216ALTA
/WE
BA0 BA1
A10
RAa
RDa
RAb
ADD
RAa
CAa
RDa
CDa
RAb
CAb
DM
L
DQS
Hi-Z VTT Hi-Z
DQ
VTT
DAa1 DAa2 DAa3 DAa4 DAa5 DAa6 DAa7 DAa8 DDa1 DDa2 DDa3 DDa4 DDa5 DDa6 DDa7 DDa8
DAb1 DAb2 DAb3 DAb4 DAb5 DAb6 DAb7 DAb8
Activate Command for Bank A
Write Command for Bank A
Activate Command for Bank D
Write Command for Bank D
Precharge Command for Bank A
Activate Command for Bank A
Write Command for Bank A Precharge Command for Bank D
59
60
Preliminary Data Sheet E0136E30
Random Row Write (Ping-Pong Banks) (2/2) (Burst Length = 8, /CAS Latency = 2.5)
T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
/CLK
CKE
H
/CS
/RAS
/CAS
EDD1204ALTA, EDD1208ALTA, EDD1216ALTA
/WE
BA0 BA1
A10
RAa
RDa
RAb
ADD L
RAa
CAa
RDa
CDa
RAb
CAb
DM
DQS VTT
Hi-Z
DQ
VTT
Hi-Z
DAa1 DAa2 DAa3 DAa4 DAa5 DAa6 DAa7 DAa8 DDa1 DDa2 DDa3 DDa4 DDa5 DDa6 DDa7 DDa8
DAb1 DAb2 DAb3 DAb4 DAb5 DAb6 DAb7 DAb8
Hi-Z
Activate Command for Bank A
Write Command for Bank A Activate Command for Bank D
Write Command for Bank D
Precharge Command for Bank A
Activate Command for Bank A Precharge Command for Bank D
Write Command for Bank A
Read and Write (1/2) (Burst Length = 8, /CAS Latency = 2)
T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21
/CLK
CKE
H
;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ; ;; ;; ;; ;; ;; ; ;; ;; ;; ; ;; ;; ;; ;; ; ;; ; ;; ; ;; ;; ;;; ; ;; ; ;;; ; ;; ;; ;; ; ;; ; ;;; ; ;; ;; ;; ; ;; ; ;;; ; ;; ;; ;; ; ;; ; ;;; ; ;; ;; ;; ; ;;; ;;; ; ; ;; ;; ; ;; ;; ;; ;; ;; ;;; ;; ; ; ;; ;; ;; ;; ;; ;; ;; ;; ; ;;
/CS /RAS /CAS
Preliminary Data Sheet E0136E30
EDD1204ALTA, EDD1208ALTA, EDD1216ALTA
/WE
BA0
BA1
A10
RAa
ADD
RAa
CAa
CAb
CAc
DM
Word Masking
DQS
VTT
Hi-Z
DQ
VTT
Hi-Z
QAa1 QAa2 QAa3 QAa4 QAa5 QAa6 QAa7 QAa8
DAb1
DAb3 DAb4 DAb5 DAb6 DAb7 DAb8
QAc1 QAc2 QAc3 QAc4 QAc5 QAc6 QAc7 QAc8
Activate Command for Bank A
Read Command for Bank A
Hi-Z at the end of wrap function
Write Command for Bank A
Read Command for Bank A
61
0-Clock Latency
62
Preliminary Data Sheet E0136E30
Read and Write (2/2) (Burst Length = 8, /CAS Latency = 2.5)
T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21
;; ;; ;; ;;; ;; ;; ;; ;; ;; ;;; ;; ;; ;; ;; ;; ;;; ;; ;; ;; ;; ;; ;;; ;; ;; ;; ;; ;; ;;; ;; ;; ;; ;; ;; ;;; ;; ;; ; ;; ;; ;;; ;; ;; ;; ;; ;; ;; ;; ;; ; ;; ; ;; ;; ;; ;;; ; ; ; ;; ; ;; ;; ;; ;;;; ; ;; ; ;; ;; ;; ;;;; ; ;; ;; ;; ;; ;;; ; ; ;; ;; ;; ;; ;;; ; ; ;; ;; ;; ;; ; ;;; ; ; ;; ; ; ;; ;; ;; ; ;; ; ;; ;; ;; ;; ;;;; ; ;; ;; ;; ;; ; ;;;; ; ;; ;; ;; ; ;; ;; ;; ;;; ; ; ;; ;; ;; ;; ;;;; ; ;; ; ; ;; ;; ;;
/CLK CKE H /CS /RAS /CAS
EDD1204ALTA, EDD1208ALTA, EDD1216ALTA
/WE
BA0
BA1
A10
RAa
ADD
RAa
CAa
CAb
CAc
DM
Word Masking
DQS
VTT
Hi-Z
DQ
VTT
Hi-Z
QAa1 QAa2 QAa3 QAa4 QAa5 QAa6 QAa7 QAa8
DAb1
DAb3 DAb4 DAb5 DAb6 DAb7 DAb8
QAc1 QAc2 QAc3
Activate Command for Bank A
Read Command for Bank A
Write Command for Bank A
Read Command for Bank A
0-Clock Latency
Interleaved Column Read Cycle (1/2) (Burst Length = 8, /CAS Latency = 2)
T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21
/CLK
CKE
H
/CS
;; ;; ; ;; ;; ;; ;; ;; ;; ; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ; ;; ;; ;; ;; ;; ;; ;;; ;; ;; ; ;; ; ;; ;; ; ;; ;; ;; ; ;; ;; ;; ; ;; ;; ; ; ;; ;; ;; ;; ; ;; ;; ;; ; ;; ;; ;; ;; ; ;; ;; ;; ;; ; ; ; ;; ;; ;; ;; ; ;; ;; ; ; ; ;; ;; ; ; ; ;; ;; ;; ;; ; ;; ;; ;; ;; ;; ; ;; ; ;; ;; ;; ;; ; ;; ; ;; ; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;;; ;; ;; ;; ;; ;;; ;; ;; ;; ;; ;;;
/RAS /CAS
Preliminary Data Sheet E0136E30
EDD1204ALTA, EDD1208ALTA, EDD1216ALTA
/WE
BA0
BA1
A10
RAa
RDa
ADD
RAa
CAa
RDa
CDa
CDb
CDc
CAb
CDd
DQM
Hi-Z
DQS
VTT VTT
DQ
Hi-Z
Aa1 Aa2 Aa3 Aa4 Aa5 Aa6 Aa7 Aa8 Da1 Da2 Da3 Da4 Db1 Db2 Db3 Db4 Dc1 Dc2 Dc3 Dc4 Ab1 Ab2 Ab3 Ab4 Dd1 Dd2 Dd3 Dd4 Dd5 Dd6 Dd7 Dd8
Activate Command for Bank A
Read Command for Bank A
Activate Command for bank D
Read Command for Bank D
Read Command for Bank D
Read Command for Bank D
Read Command for Bank A
Read Command for Bank D Precharge Command for Bank A
Precharge Command for Bank D
63
64
Preliminary Data Sheet E0136E30
Interleaved Column Read Cycle (2/2) (Burst Length = 8, /CAS Latency = 2.5)
T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21
/CLK
;;; ;; ; ;;; ;; ;; ; ; ;;; ;; ;; ; ; ; ;;; ;; ;; ; ; ; ; ;;; ;; ;; ; ; ; ;;; ;; ;; ; ; ; ;;; ;; ;; ;; ; ;; ;; ;; ; ; ; ;;; ;; ;; ; ; ;; ;; ;; ; ; ; ;;; ;; ;; ; ;; ;; ; ; ;;; ;; ;; ; ; ;; ;; ;; ;; ; ; ;;; ;; ;; ; ;; ;;; ;; ;; ; ;; ;;; ;; ;; ;;; ;; ;;; ;; ;; ; ;;; ;; ;; ; ; ;;; ;; ;; ; ;; ;;; ;; ;; ;; ;;
CKE H /CS /RAS /CAS
EDD1204ALTA, EDD1208ALTA, EDD1216ALTA
/WE
BA0
BA1
A10
RAa
RDa
ADD
RAa
CAa
RDa
CDa
CDb
CDc
CAb
DQM
L
DQS DQ
VTT
Hi-Z
VTT
Hi-Z
Aa1 Aa2 Aa3 Aa4 Aa5 Aa6 Aa7 Aa8 Da1 Da2 Da3 Da4 Db1 Db2 Db3 Db4 Dc1 Dc2 Dc3 Dc4 Ab1 Ab2 Ab3 Ab4 Ab5 Ab6 Ab7 Ab8
Activate Command for Bank A
Read Command for Bank A Activate Command for Bank D
Read Command for Bank D
Read Command for Bank D
Read Command for Bank D
Read Command for Bank A Precharge Command for Bank D Precharge Command for Bank A
Interleaved Column Write Cycle (1/2) (Burst Length = 8, /CAS Latency = 2)
T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
/CLK CKE H
/CS
/RAS
/CAS
Preliminary Data Sheet E0136E30
EDD1204ALTA, EDD1208ALTA, EDD1216ALTA
/WE
BA0
BA1
A10
RAa
RBa
ADD
RAa
CAa
RBa
CBa
CBb
CBc
CAb
CBd
DM Hi-Z
DQS
VTT
DQ
VTT
Hi-Z Aa1 Aa2 Aa3 Aa4 Aa5 Aa6 Aa7 Aa8 Ba1 Ba2 Ba3 Ba4 Bb1 Bb2 Bb3 Bb4 Bc1 Bc2 Bc3 Bc4 Ab1 Ab2 Ab3 Ab4 Bd1 Bd2 Bd3 Bd4 Bd5 Bd6 Bd7 Bd8
Activate Command for Bank A
Write Command for Bank A Activate Command for Bank B
Write Command for Bank B
Write Command for Bank B
Write Command for Bank B
Write Command for Bank A
Write Command for Bank B Precharge Command for Bank A Precharge Command for Bank B
65
66
Preliminary Data Sheet E0136E30
Interleaved Column Write Cycle (2/2) (Burst Length = 8, /CAS Latency = 2.5)
T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
/CLK
CKE
H
/CS
/RAS
/CAS
EDD1204ALTA, EDD1208ALTA, EDD1216ALTA
/WE BA0
BA1
A10
RAa RAa CAa
RBa RBa CBa CBb CAb CBd
ADD
CBc
DQM Hi-Z DQS
VTT
DQ
VTT
Hi-Z
Aa1 Aa2 Aa3 Aa4 Aa5 Aa6 Aa7 Aa8 Ba1 Ba2 Ba3 Ba4 Bb1 Bb2 Bb3 Bb4 Bc1 Bc2 Bc3 Bc4 Ab1 Ab2 Ab3 Ab4 Bd1 Bd2 Bd3 Bd4 Bd5 Bd6 Bd7 Bd8
Activate Command for Bank A
Write Command for Bank A Activate Command for Bank B
Write Command for Bank B
Write Command for Bank B
Write Command for Bank B
Write Command for Bank A
Write Command for Bank B Precharge Command for Bank A Precharge Command for Bank B
Auto Precharge after Read Burst (1/2) (Burst Length = 8, /CAS Latency = 2)
T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21
;; ; ;;; ; ;; ; ;; ; ;;;; ; ;; ; ;; ; ;;;; ; ;; ; ;; ; ;;;; ; ;; ;; ;; ;; ;; ;; ; ;;;; ; ;; ;; ; ; ;; ; ; ;;;; ; ;; ;; ;; ; ; ;; ; ; ;;;; ; ;; ; ;; ;; ; ; ; ;;;; ; ;;; ;;; ; ;; ;; ;; ; ; ;; ;; ; ;;;; ; ;; ;; ; ; ;;;; ; ;; ;; ; ; ;;;; ; ;; ;; ; ; ;; ;; ;; ;; ;; ; ;;;; ; ;; ;; ; ;; ; ; ; ;;;; ; ;; ;; ;; ; ; ; ;; ; ;;;; ; ; ;; ;; ;; ; ; ;;;; ; ; ; ;;; ; ;; ;; ;; ; ;;;; ; ;; ;; ; ; ; ;;;; ; ;; ; ;; ; ; ;; ;
/CLK CKE H /CS /RAS /CAS
Preliminary Data Sheet E0136E30
EDD1204ALTA, EDD1208ALTA, EDD1216ALTA
/WE
BA0
BA1
A10
RAa
RDa
RDb
RAc
ADD
RAa
CAa
RDa
CDa
CAb
RDb
CDb
RAc
CAc
DM
Hi-Z DQS VTT VTT Hi-Z
DQ
Activate Command for Bank A
Activate Command for Bank D Bank D Read Command with Auto Precharge
Bank A Read Command without Auto Precharge
Bank A Read Command with Auto Precharge Auto Precharge Start for Bank D
Activate Command for Bank D
Activate Command for Bank A Auto Precharge Start for Bank D Bank D Read Command with Auto Precharge Bank A Read Command with Auto Precharge
Auto Precharge Start for Bank A
67
68
Preliminary Data Sheet E0136E30
Auto Precharge after Read Burst (2/2) (Burst Length = 8, /CAS Latency = 2.5)
T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21
;;; ; ;; ;; ;;;; ; ;; ; ;; ; ;;;; ; ;; ; ;; ; ;;;; ; ; ;; ; ;; ;;;; ; ; ; ;; ; ;; ;;;; ; ;; ;; ; ; ; ; ;;;; ; ;; ;; ; ; ; ;;;; ; ;; ; ;; ;; ; ; ;;;; ; ;; ;; ; ; ;; ; ; ;;;; ; ;; ;; ; ; ;;;; ; ; ;; ;; ;; ;; ; ;; ;; ; ;;;; ; ; ;; ;; ; ; ;;;; ; ; ;; ;; ; ;;;; ; ; ;; ;; ; ; ; ;;;; ; ; ;; ;; ; ;;;; ; ;; ;; ; ;;; ; ;; ;; ;; ;;;; ; ;; ; ;; ; ;; ;
/CLK CKE H /CS /RAS /CAS
EDD1204ALTA, EDD1208ALTA, EDD1216ALTA
/WE
BA0
BA1
A10
RAa
RDa
RDb
ADD
RAa
CAa
RDa
CDa
CAb
RDb
CDb
DM
DQS VTT
Hi-Z
DQ
VTT
Hi-Z
Activate Command for Bank A
Activate Command for Bank D Bank A Read Command without Auto Precharge Bank D Read Command with Auto Precharge
Bank A Read Command with Auto Precharge
Auto Precharge Start for Bank A
Bank D Read Command with Auto Precharge
Auto Precharge Start for Bank D
Activate Command for Bank D
Auto Precharge after Write Burst (1/2) (Burst Length = 8, /CAS Latency = 2)
T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
/CLK CKE
H
/CS
/RAS
/CAS
Preliminary Data Sheet E0136E30
EDD1204ALTA, EDD1208ALTA, EDD1216ALTA
/WE
BA0
BA1
A10
RAa
RDa
RDb
RAc
ADD
RAa
CAa
RDa
CDa
CAb
RDb
CDb
RAc
CAc
DM
L Hi-Z
DQS
VTT
DQ
VTT
Hi-Z
Activate Command for Bank A
Activate Command for Bank D Bank D Write Command with Auto Precharge Bank A Write Command with Auto Precharge
Activate Command for Bank D Bank D Write Command with Auto Precharge Auto Precharge Start for Bank D
Activate Command for Bank A Bank A Write Command with Auto Precharge
Bank A Write Command without Auto Precharge
Auto Precharge Start for Bank A
69
70
Preliminary Data Sheet E0136E30
Auto Precharge after Write Burst (2/2) (Burst Length = 8, /CAS Latency = 2.5)
T0 CLK /CLK T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CKE
H
/CS
/RAS /CAS
EDD1204ALTA, EDD1208ALTA, EDD1216ALTA
/WE
BA0
BA1 RAa RDa RDb
A10
ADD DM
RAa
CAa
RDa
CDa
CAb
RDb
CDb
DQS
VTT
Hi-Z
DQ
VTT
Hi-Z
Activate Command for Bank A
Activate Command for Bank D Bank A Write Command without Auto Precharge Bank D Write Command with Auto Precharge
Bank A Write Command with Auto Precharge
Activate Command for Bank D
Bank D Write Command with Auto Precharge
Auto Precharge Start for Bank D
Auto Precharge Start for Bank A
Byte Write Operation (Burst Length = 8, /CAS Latency = 2)
Lower DQ
Upper DQ
UDQS
LDQS
/RAS
/CAS
UDM
/CLK
ADD
LDM
CKE
CLK
BA0
BA1
/WE
A10
/CS
;;; ; ;; ; ;;;; ;; ;; ; ;; ; ;;;; ;; ;; ; ;; ; ;;;; ;; ;; ; ;; ; ;;;; ;; ;; ; ;; ; ;;;; ;; ;; ;; ; ;; ;; ;; ;; ; ;;;; ;; ;; ;; ; ; ; ;;;; ;; ;; ; ;; ; ;;;; ; ;; ;; ; ;;;; ; ;; ;; ; ;;;; ;; ;; ;; ; ; ; ;;;; ;; ;; ;; ; ; ;;;; ;; ;; ; ;; ; ;;;; ;; ;; ; ;; ; ;;;; ;; ; ;; ;; ;; ;; ;; ;;;; ;; ; ;; ; ;; ;;;; ;; ;; ; ;; ;; ;; ;
Hi-Z Hi-Z Hi-Z Hi-Z
VTT VTT VTT VTT
EDD1204ALTA, EDD1208ALTA, EDD1216ALTA
T15
T16
T17
T18
T19
T20
T21
T14
T3
T4
T5
T6
T7
T8
T9
T1
Activate Command
T0
H
Read Command
T2
Lower Byte Lower Byte not Write not Write Upper Byte not Write
T10
T11
T12
T13
Preliminary Data Sheet E0136E30
Read Command
71
72
Preliminary Data Sheet E0136E30
PRE (Precharge) Termination of Burst (1/2) (Burst Length = 8, /CAS Latency = 2)
T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21
/CLK
;;; ;; ; ;;; ; ;; ; ;; ;;; ; ;; ; ;; ;;; ; ;; ; ;; ;;; ; ;; ; ;; ;; ; ;; ;;; ; ;; ;; ; ;;; ; ;; ; ;; ;;; ; ;; ; ;; ;;; ; ;; ; ; ;; ; ;; ; ; ;;; ; ;; ; ;; ;;; ; ;; ; ;; ;;; ; ; ;; ; ;; ; ;;; ; ;; ; ; ;; ; ;;; ; ;; ; ;; ;;; ; ;; ; ;; ;;; ; ;; ; ;; ;; ; ;; ; ;; ;;; ; ;; ; ;; ;
CKE H /CS /RAS /CAS /WE BA0 BA1 A10 RAa RAb RAc ADD RAa CAa RAb CAb RAc DM Write Mask DQS VTT Hi-Z DQ VTT Hi-Z DAa1 DAa2 DAa3 DAa4 QAb1 QAb2 QAb3 QAb4 QAb5 QAb6 Activate Command for Bank A Write Command for Bank A Precharge PRE Command Command for Bank A Termination tRAS tRP Activate Command for Bank A tRAS tRP Read Command for Bank A Precharge Command for Bank A Activate Command for Bank A PRE Command Termination
EDD1204ALTA, EDD1208ALTA, EDD1216ALTA
PRE (Precharge) Termination of Burst (2/2) (Burst Length = 8, /CAS Latency = 2.5)
T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21
; ;; ; ;;; ; ; ;; ; ;;;;;; ; ;; ; ;; ; ;; ; ;;;;;; ;; ; ;;;;;; ;; ;; ; ;; ; ;; ; ;;;;;; ; ; ;;;;;; ;; ; ; ;;;;;; ; ;; ; ;; ; ; ;; ; ; ;;;;;; ;; ; ;; ; ;;;;;; ;; ;; ; ;;;;;; ;; ;; ; ;;;;;; ;; ;; ; ;;;;;; ; ;; ; ; ;;;;;; ; ;; ; ; ;;;;;; ; ;; ; ; ;;;;;; ; ;; ; ; ;;;;;; ;; ;; ; ;;;;;; ;;;; ;; ; ;
/CLK CKE H /CS /RAS /CAS
Preliminary Data Sheet E0136E30
EDD1204ALTA, EDD1208ALTA, EDD1216ALTA
/WE
BA0
BA1
A10
RAa
RAb
RAc
ADD
RAa
CAa
RAb
CAb
RAc
DM
Write Mask
DQS
VTT
Hi-Z
DQ
VTT
Hi-Z
DAa1 DAa2 DAa3 DAa4
QAb1 QAb2 QAb3 QAb4 QAb5 QAb6
Activate Command for Bank A
Write Command for Bank A PRE Command Termination tRAS Precharge Command for Bank A tRP Activate Command for Bank A
Read Command for Bank A
Precharge Command for Bank A
tRAS
Activate Command PRE Command for Bank A Termination tRP
73
EDD1204ALTA, EDD1208ALTA, EDD1216ALTA
14. Package Drawing
66-PIN PLASTIC TSOP (II) (10.16 mm (400))
detail of lead end 66 34 F G R
P
L S
1 A
33
E H I J
S
L K
M
C D M
N
S B
NOTES 1. Each lead centerline is located within 0.12 mm of its true position (T.P.) at maximum material condition. 2. Dimension "A" does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.15mm per side.
ITEM A B C D E F G H I J K L M N P R S MILLIMETERS 22.220.05 0.865 MAX. 0.65 (T.P.) 0.24+0.08 -0.07 0.100.05 1.10.1 1.00 11.760.20 10.160.10 0.800.2 0.145+0.025 -0.015 0.50 0.12 0.10 3+5 -3 0.25 0.600.15 S66G5-65-9LG-1
74
Preliminary Data Sheet E0136E30
EDD1204ALTA, EDD1208ALTA, EDD1216ALTA
15. Recommended Soldering Conditions
Please contact our sales offices for soldering conditions of EDD12xxALTA.
Type of Surface Mount Device
EDD12xxALTA: 66-pin Plastic TSOP (II) (10.16 mm (400))
Preliminary Data Sheet E0136E30
75
EDD1204ALTA, EDD1208ALTA, EDD1216ALTA
16. Revision History
Version / Date Ver. 1.0 / April. 2001 Ver. 2.0 / May. 2001 Page This edition
-- -- 27 29 36 41 42 46 55 56 60 65 66 69 70
Description Type of revision
-- -- Modification Modification Modification Modification Modification Modification Modification Modification Modification Modification Modification Modification Modification Addition Modification Modification Modification Modification Modification
Previous edition
-- -- 27 29 36 41 42 46 55 56 60 65 66 69 70 38 39 41 42 42 45
Location
-- -- Figure of Write to Precharge Command Interval Figure of Write with Auto precharge Figure of Precharge Termination in Write Cycle tCK (CL = 2.5) (MIN.) : 8 ns to 10 ns tWR (MIN.) : 15/15/15 ns to 2/2/2 CLK AC Parameters for Write Timing Random Column Write (1/2) Random Column Write (2/2) Random Row Write (2/2) Interleaved Column Write Cycle (1/2) Interleaved Column Write Cycle (2/2) Auto Precharge after Write Burst (1/2) Auto Precharge after Write Burst (2/2) DC Characteristics specification VIH (ac) (MIN.): VREF + 0.35 to VREF + 0.31 VIL (ac) (MAX.): VREF + 0.35 to VREF - 0.31 tHP (MIN.): tCH, tCL to MIN. (tCH, tCL) tWPRE (MIN.) (tCK = 7.5ns): 0.25 ns to 1.88 ns tDAL (MIN.): TBD to 35 ns [tDAL]: to 5/5/5/4/4/4
Ver. 3.0 October 2001
38 39 41 42 42 45
76
Preliminary Data Sheet E0136E30
EDD1204ALTA, EDD1208ALTA, EDD1216ALTA
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR MOS DEVICES
Exposing the MOS devices to a strong electric field can cause destruction of the gate oxide and ultimately degrade the MOS devices operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it, when once it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. MOS devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. MOS devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor MOS devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS DEVICES
No connection for CMOS devices input pins can be a cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. The unused pins must be handled in accordance with the related specifications.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Power-on does not necessarily define initial status of MOS devices. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the MOS devices with reset function have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. MOS devices are not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for MOS devices having reset function.
CME0107
Preliminary Data Sheet E0136E30
77
EDD1204ALTA, EDD1208ALTA, EDD1216ALTA
The information in this document is subject to change without notice. Before using this document, confirm that this is the latest version.
No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Elpida Memory, Inc. Elpida Memory, Inc. does not assume any liability for infringement of any intellectual property rights (including but not limited to patents, copyrights, and circuit layout licenses) of Elpida Memory, Inc. or third parties by or arising from the use of the products or information listed in this document. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of Elpida Memory, Inc. or others. Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of the customer's equipment shall be done under the full responsibility of the customer. Elpida Memory, Inc. assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. [Product applications] Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability. However, users are instructed to contact Elpida Memory's sales office before using the product in aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment, medical equipment for life support, or other such application in which especially high quality and reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk of bodily injury. [Product usage] Design your application so that the product is used within the ranges and conditions guaranteed by Elpida Memory, Inc., including the maximum ratings, operating supply voltage range, heat radiation characteristics, installation conditions and other related characteristics. Elpida Memory, Inc. bears no responsibility for failure or damage when the product is used beyond the guaranteed ranges and conditions. Even within the guaranteed ranges and conditions, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Elpida Memory, Inc. products does not cause bodily injury, fire or other consequential damage due to the operation of the Elpida Memory, Inc. product. [Usage environment] This product is not designed to be resistant to electromagnetic waves or radiation. This product must be used in a non-condensing environment. If you export the products or technology described in this document that are controlled by the Foreign Exchange and Foreign Trade Law of Japan, you must follow the necessary procedures in accordance with the relevant laws and regulations of Japan. Also, if you export products/technology controlled by U.S. export control regulations, or another country's export control laws or regulations, you must follow the necessary procedures in accordance with such laws or regulations. If these products/technology are sold, leased, or transferred to a third party, or a third party is granted license to use these products, that third party must be made aware that they are responsible for compliance with the relevant laws and regulations.
M01E0107

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